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Revert "Closer to getting subword write misaligned working."

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This reverts commit 6a9c2d8dc4.
This commit is contained in:
Rose Thompson 2024-03-06 15:16:43 -06:00
parent dce7de59a3
commit 9668fdd868
2 changed files with 2 additions and 9 deletions
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2
src/lsu/lsu.sv
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@ -424,7 +424,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if(MISALIGN_SUPPORT) begin
subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .CacheableM, .IMAFWriteDataM, .LittleEndianWriteDataM);
subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .IMAFWriteDataM, .LittleEndianWriteDataM);
end else begin
subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);

9
src/lsu/subwordwritedouble.sv
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@ -33,7 +33,6 @@ module subwordwritedouble #(parameter LLEN) (
input logic [2:0] PAdrM,
input logic FpLoadStoreM,
input logic BigEndianM,
input logic CacheableM,
input logic [LLEN-1:0] IMAFWriteDataM,
output logic [LLEN*2-1:0] LittleEndianWriteDataM
);
@ -44,13 +43,7 @@ module subwordwritedouble #(parameter LLEN) (
logic [4:0] LengthM;
// Funct3M[2] is the unsigned bit. mask upper bits.
// Funct3M[1:0] is the size of the memory access.
// cacheable, BigEndian
// 10: PAdrM[2:0]
// 11: BigEndianPAdr
// 00: 00000
// 01: 00111
mux4 #(5) OffsetMux(5'b0, 5'b11111, {2'b0, PAdrM}, BigEndianPAdr, {CacheableM, BigEndianM}, PAdrSwap);
//assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
/* verilator lint_off WIDTHEXPAND */
/* verilator lint_off WIDTHTRUNC */
assign BigEndianPAdr = (LLEN/4) - PAdrM - LengthM;