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Reordered Zicond support in ALU

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This commit is contained in:
David Harris 2024-05-22 08:29:08 -07:00
parent a17204b0fe
commit 3ad815ce34
1 changed files with 16 additions and 15 deletions
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31
src/ieu/alu.sv
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@ -60,7 +60,22 @@ module alu import cvw::*; #(parameter cvw_t P) (
// CondShiftA is A for add/sub or a shifted version of A for shift-and-add BMU instructions
assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(P.XLEN-1){1'b0}}, SubArith};
// Zicond block conditionally zeros B
if (P.ZICOND_SUPPORTED) begin: zicond
logic BZero;
assign BZero = (B == 0); // check if rs2 = 0
// Create a signal that is 0 when czero.* instruction should clear result
// If B = 0 for czero.eqz or if B != 0 for czero.nez
always_comb
case (CZero)
2'b01: ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
2'b10: ZeroCondMaskInvB = {P.XLEN{BZero}}; // czero.nez: kill if B != 0
default: ZeroCondMaskInvB = CondMaskInvB; // otherwise normal behavior
endcase
end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
// Shifts (configurable for rotation)
shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
@ -105,18 +120,4 @@ module alu import cvw::*; #(parameter cvw_t P) (
assign CondShiftA = A;
end
// Zicond block
if (P.ZICOND_SUPPORTED) begin: zicond
logic BZero;
assign BZero = (B == 0); // check if rs2 = 0
// Create a signal that is 0 when czero.* instruction should clear result
// If B = 0 for czero.eqz or if B != 0 for czero.nez
always_comb
case (CZero)
2'b01: ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
2'b10: ZeroCondMaskInvB = {P.XLEN{BZero}}; // czero.nez: kill if B != 0
default: ZeroCondMaskInvB = CondMaskInvB; // otherwise normal behavior
endcase
end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
endmodule