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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Renamed CacheHit to Hit.
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parent
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commit
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6
src/cache/cache.sv
vendored
6
src/cache/cache.sv
vendored
@ -82,7 +82,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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logic ClearDirty, SetDirty, SetValid, ClearValid;
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logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
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logic [NUMWAYS-1:0] HitWay, ValidWay;
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logic CacheHit;
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logic Hit;
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logic [NUMWAYS-1:0] VictimWay, DirtyWay, HitDirtyWay;
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logic LineDirty, HitLineDirty;
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logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0];
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@ -132,7 +132,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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end else
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assign VictimWay = 1'b1; // one hot.
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assign CacheHit = |HitWay;
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assign Hit = |HitWay;
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assign LineDirty = |DirtyWay;
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assign HitLineDirty = |HitDirtyWay;
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@ -226,7 +226,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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.FlushStage, .CacheRW, .Stall,
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.CacheHit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted,
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.Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim,
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.ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
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16
src/cache/cachefsm.sv
vendored
16
src/cache/cachefsm.sv
vendored
@ -50,7 +50,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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output logic CacheAccess, // Cache access
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// cache internals
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input logic CacheHit, // Exactly 1 way hits
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input logic Hit, // Exactly 1 way hits
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input logic LineDirty, // The selected line and way is dirty
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input logic HitLineDirty, // The cache hit way is dirty
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input logic FlushAdrFlag, // On last set of a cache flush
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@ -92,17 +92,17 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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statetype CurrState, NextState;
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assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
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assign AnyUpdateHit = (CacheRW[0]) & CacheHit; // exclusion-tag: icache storeAMO1
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assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); // exclusion-tag: icache AnyUpdateHit
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assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~Hit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
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assign AnyUpdateHit = (CacheRW[0]) & Hit; // exclusion-tag: icache storeAMO1
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assign AnyHit = AnyUpdateHit | (CacheRW[1] & Hit); // exclusion-tag: icache AnyUpdateHit
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assign CMOZeroNoEviction = CMOpM[3] & ~LineDirty; // (hit or miss) with no writeback store zeros now
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assign CMOWriteback = ((CMOpM[1] | CMOpM[2]) & CacheHit & HitLineDirty) | CMOpM[3] & LineDirty;
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assign CMOWriteback = ((CMOpM[1] | CMOpM[2]) & Hit & HitLineDirty) | CMOpM[3] & LineDirty;
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assign FlushFlag = FlushAdrFlag & FlushWayFlag;
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// outputs for the performance counters.
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assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
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assign CacheMiss = CacheAccess & ~CacheHit;
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assign CacheMiss = CacheAccess & ~Hit;
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// special case on reset. When the fsm first exists reset twayhe
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// PCNextF will no longer be pointing to the correct address.
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@ -169,7 +169,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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// Flush and eviction controls
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CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2]) & CacheBusAck;
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assign SelVictim = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOpM[1] | CMOpM[2])) | (CacheBusAck & CMOpM[3]))) |
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(CurrState == STATE_ACCESS & ((AnyMiss & LineDirty) | (CMOZeroNoEviction & ~CacheHit))) |
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(CurrState == STATE_ACCESS & ((AnyMiss & LineDirty) | (CMOZeroNoEviction & ~Hit))) |
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(CurrState == STATE_WRITE_LINE);
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assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2] | ~CacheBusAck)) |
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(CurrState == STATE_ACCESS & AnyMiss & LineDirty);
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@ -188,7 +188,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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(CurrState == STATE_WRITEBACK & CacheBusAck & ~(|CMOpM));
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logic LoadMiss;
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assign LoadMiss = (CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
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assign LoadMiss = (CacheRW[1]) & ~Hit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
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assign CacheBusRW[0] = (CurrState == STATE_ACCESS & LoadMiss & LineDirty) | // exclusion-tag: icache CacheBusW
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(CurrState == STATE_WRITEBACK & ~CacheBusAck) |
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