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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
ZAAMO and ZALRSC implemented but not tested
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@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 0;
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localparam ZAAMO_SUPPORTED = 0;
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localparam ZALRSC_SUPPORTED = 0;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 1;
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@ -52,6 +52,8 @@ localparam ZICOND_SUPPORTED = 1;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 1;
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localparam ZAAMO_SUPPORTED = 0;
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localparam ZALRSC_SUPPORTED = 0;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 1;
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@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 0;
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localparam ZAAMO_SUPPORTED = 0;
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localparam ZALRSC_SUPPORTED = 0;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 0;
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@ -50,6 +50,8 @@ localparam ZICOND_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 0;
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localparam ZAAMO_SUPPORTED = 0;
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localparam ZALRSC_SUPPORTED = 0;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 1;
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@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 1;
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localparam SVPBMT_SUPPORTED = 1;
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localparam SVNAPOT_SUPPORTED = 1;
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localparam SVINVAL_SUPPORTED = 1;
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localparam ZAAMO_SUPPORTED = 0;
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localparam ZALRSC_SUPPORTED = 0;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 1;
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@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 0;
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localparam ZAAMO_SUPPORTED = 0;
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localparam ZALRSC_SUPPORTED = 0;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 0;
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@ -31,6 +31,8 @@ localparam cvw_t P = '{
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SVPBMT_SUPPORTED : SVPBMT_SUPPORTED,
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SVNAPOT_SUPPORTED : SVNAPOT_SUPPORTED,
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SVINVAL_SUPPORTED : SVINVAL_SUPPORTED,
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ZAAMO_SUPPORTED : ZAAMO_SUPPORTED,
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ZALRSC_SUPPORTED : ZALRSC_SUPPORTED,
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BUS_SUPPORTED : BUS_SUPPORTED,
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DCACHE_SUPPORTED : DCACHE_SUPPORTED,
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ICACHE_SUPPORTED : ICACHE_SUPPORTED,
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@ -66,6 +66,8 @@ typedef struct packed {
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logic SVPBMT_SUPPORTED;
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logic SVNAPOT_SUPPORTED;
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logic SVINVAL_SUPPORTED;
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logic ZAAMO_SUPPORTED;
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logic ZALRSC_SUPPORTED;
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// Microarchitectural Features
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logic BUS_SUPPORTED;
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@ -265,12 +265,12 @@ module controller import cvw::*; #(parameter cvw_t P) (
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ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores
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7'b0100111: if (FLSFunctD)
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ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported
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7'b0101111: if (P.A_SUPPORTED & AFunctD) begin
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if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
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7'b0101111: if (AFunctD) begin
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if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
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ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr
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else if (InstrD[31:27] == 5'b00011)
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else if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00011)
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ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc
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else if (AMOFunctD)
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else if ((P.A_SUPPORTED | P.ZAAMO_SUPPORTED) & AMOFunctD)
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ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo
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end
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7'b0110011: if (RFunctD)
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@ -139,6 +139,6 @@ module datapath import cvw::*; #(parameter cvw_t P) (
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mux5 #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW);
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// handle Store Conditional result if atomic extension supported
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if (P.A_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
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else assign SCResultW = '0;
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if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
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else assign SCResultW = '0;
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endmodule
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@ -48,11 +48,20 @@ module atomic import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] AMOResultM;
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logic MemReadM;
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amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
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mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
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assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
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lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
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// AMO ALU
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if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) begin
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amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
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mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
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end else
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assign IMAWriteDataM = IHWriteDataM;
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// LRSC unit
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if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) begin
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assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
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lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
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end else begin
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assign SquashSCW = 0;
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assign LSURWM = PreLSURWM;
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end
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endmodule
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@ -397,7 +397,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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// Atomic operations
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (P.A_SUPPORTED) begin:atomic
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if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic
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atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM,
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.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
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.IMAWriteDataM, .SquashSCW, .LSURWM);
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@ -67,6 +67,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
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assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
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assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
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assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
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assert (P.A_SUPPORTED + P.ZAAMO_SUPPORTED + P.ZALRSC_SUPPORTED < 2) else $fatal(1, "At most one of A, Zaamo, or Zalrsc can be supported");
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end
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endmodule
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