ZAAMO and ZALRSC implemented but not tested

config/rv32e/config.vh

@@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv32gc/config.vh

@@ -52,6 +52,8 @@ localparam ZICOND_SUPPORTED = 1;
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 1;
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv32i/config.vh

@@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 0;

config/rv32imc/config.vh

@@ -50,6 +50,8 @@ localparam ZICOND_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv64gc/config.vh

@@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 1;
 localparam SVPBMT_SUPPORTED = 1;
 localparam SVNAPOT_SUPPORTED = 1;
 localparam SVINVAL_SUPPORTED = 1;
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv64i/config.vh

@@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 0;

config/shared/parameter-defs.vh

@@ -31,6 +31,8 @@ localparam cvw_t P = '{
   SVPBMT_SUPPORTED :     SVPBMT_SUPPORTED,
   SVNAPOT_SUPPORTED :    SVNAPOT_SUPPORTED,
   SVINVAL_SUPPORTED :    SVINVAL_SUPPORTED,
+  ZAAMO_SUPPORTED :      ZAAMO_SUPPORTED,
+  ZALRSC_SUPPORTED :     ZALRSC_SUPPORTED, 
   BUS_SUPPORTED :        BUS_SUPPORTED,
   DCACHE_SUPPORTED :     DCACHE_SUPPORTED,
   ICACHE_SUPPORTED :     ICACHE_SUPPORTED,

src/cvw.sv

@@ -66,6 +66,8 @@ typedef struct packed {
   logic         SVPBMT_SUPPORTED;
   logic         SVNAPOT_SUPPORTED;
   logic         SVINVAL_SUPPORTED;
+  logic         ZAAMO_SUPPORTED;
+  logic         ZALRSC_SUPPORTED;
 
   // Microarchitectural Features
   logic         BUS_SUPPORTED;

src/ieu/controller.sv

@@ -265,12 +265,12 @@ module controller import cvw::*;  #(parameter cvw_t P) (
                       ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores
       7'b0100111: if (FLSFunctD)
                       ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported
-      7'b0101111: if (P.A_SUPPORTED & AFunctD) begin
-                    if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
+      7'b0101111: if (AFunctD) begin
+                    if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
                       ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr
-                    else if (InstrD[31:27] == 5'b00011)
+                    else if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00011)
                       ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc
-                    else if (AMOFunctD) 
+                    else if ((P.A_SUPPORTED | P.ZAAMO_SUPPORTED) & AMOFunctD) 
                       ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo
                  end
       7'b0110011: if (RFunctD)

src/ieu/datapath.sv

@@ -139,6 +139,6 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   mux5  #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 
  
   // handle Store Conditional result if atomic extension supported
-  if (P.A_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
-  else               assign SCResultW = '0;
+  if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
+  else                                    assign SCResultW = '0;
 endmodule

src/lsu/atomic.sv

@@ -48,11 +48,20 @@ module atomic import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]          AMOResultM;
   logic                       MemReadM;
 
-  amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
-
-  mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
-  assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
-
-  lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
+  // AMO ALU
+  if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) begin
+    amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
+    mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
+  end else 
+    assign IMAWriteDataM = IHWriteDataM;
+  
+  // LRSC unit
+  if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) begin
+    assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
+    lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
+  end else begin
+    assign SquashSCW = 0;
+    assign LSURWM = PreLSURWM;
+  end
 
 endmodule  

src/lsu/lsu.sv

@@ -397,7 +397,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   // Atomic operations
   /////////////////////////////////////////////////////////////////////////////////////////////
  
-  if (P.A_SUPPORTED) begin:atomic
+  if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic
     atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, 
       .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, 
       .IMAWriteDataM, .SquashSCW, .LSURWM);

testbench/common/riscvassertions.sv

@@ -67,6 +67,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
     assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");   
     assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
+    assert (P.A_SUPPORTED + P.ZAAMO_SUPPORTED + P.ZALRSC_SUPPORTED < 2) else $fatal(1, "At most one of A, Zaamo, or Zalrsc can be supported");
   end
 
 endmodule