Rose Thompson
d8fe68b912
Merge pull request #1011 from davidharrishmc/dev
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Fixed bug causing Issue 1010 and made some changes to Wally privileged fields to match ImperasDV
2024-10-14 11:10:21 -05:00
David Harris
43162aa088
Fixed handling writing reserved 10 value to mstatus.mpp
2024-10-14 08:42:52 -07:00
David Harris
5ef5633a62
Adjusted menvcfg.CBIE reserved 10 behavior to match ImperasDV; spec is ambiguous (riscv-isa-manual Issue #1682
2024-10-14 05:31:59 -07:00
Jordan Carlin
e7b9369f7f
Merge pull request #1008 from davidharrishmc/dev
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Fix mcountinhibit bit 1 that should be hardwired to 0
2024-10-13 22:44:35 -07:00
David Harris
9ef211b40d
mcountinhibit bit 1 should be hardwired to 0. Discovered during functional coverage testing
2024-10-13 20:59:01 -07:00
Rose Thompson
5011084d40
Revert "This is a better solution. It's closer to the original book HPTW FSM,"
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This actually adds to the critical path and it's more complex than I feel comfortable.
This reverts commit 1ded4a972f
2024-10-11 17:02:51 -05:00
Rose Thompson
1ded4a972f
This is a better solution. It's closer to the original book HPTW FSM,
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but is slightly more complex in RTL. Instead it looks at ReadDataM
for the PTE for PBMT faults. I was worried this would cause critical
path issues but I think it is ok. ReadDataM is used only to created
PBMT and this directly controlls the enable to a flop and the state
inputs to the FSM.
2024-10-11 16:47:18 -05:00
Rose Thompson
4c7eb1d11f
Renamed IgnoreRequestTLB to HPTWFlushW and IgnoreRequest to LSUFlushW.
2024-10-11 15:41:40 -05:00
Rose Thompson
37d3db916b
Resolved the HPTW's not taking the PBMT fault on the right cycle by
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having the fsm branch to fault on any cycle a HPTWFaultM occurs. This
of course changes the figure in the book but it really relevant to
PBMT. This appeared to work because the HPTW happened to also generate
an access fault at the end of the walk and the logic produced both
faults. I wrote new test which confirms just the one is generated.
2024-10-11 15:31:20 -05:00
Rose Thompson
7a92d41ef5
Simplified logic around IgnoreRequest and HPTWFaultM.
2024-10-11 14:41:52 -05:00
Rose Thompson
fe5f342d2f
Does not work. But there is a bug hiding the IgnoreRequest confusion.
2024-10-11 12:07:26 -05:00
Rose Thompson
6a905aa2f2
Possible start to resolution on issue #839 .
2024-10-10 17:14:27 -05:00
Rose Thompson
943f6b680e
LSU cleanup.
2024-10-02 17:38:22 -05:00
Rose Thompson
35693eb7cc
Fixed bug so AMO access faults only produce StoreAmoAccessFault and
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not both LoadAccessFault adn StoreAmoAccessFault.
2024-10-02 14:04:01 -05:00
Rose Thompson
2112c705a4
Supress misaligned faults during a tlb miss. Still needs to be tested.
2024-09-30 15:55:46 -05:00
David Harris
7f0c2662b3
Merge pull request #966 from ross144/main
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Updates wsim to fail with invalid --lockstep parameters
2024-09-26 08:48:42 -07:00
Rose Thompson
1345a0f315
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-09-24 10:13:50 -05:00
David Harris
468e48899a
Remove outdated code
2024-09-23 06:06:26 -07:00
Rose Thompson
32624bc6ee
Relocated a logic in a file to avoid a future merge conflict.
2024-09-05 12:50:09 -07:00
Rose Thompson
005ea52b72
Added missing signal declaration for SPI.
2024-09-05 12:20:06 -07:00
Rose Thompson
ac047a04fa
Fixed bug in SPI with the help of Naiche and Jacob. Have yet to test
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if SPI will now run correctly with div=0 (SYSTEMCLOCK/2), but the SPI
flash card now correctly loads into the Linux OS and mount and is
reading and writting without error.
2024-09-04 17:51:48 -07:00
naichewa
3b7661dfd5
SckDiv Zero bug fixes
2024-09-03 14:58:46 -07:00
Rose Thompson
418bc6b23c
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 16:24:10 -07:00
Rose Thompson
faffecf891
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 11:02:17 -07:00
Rose Thompson
01b623b8c4
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 11:02:08 -07:00
Rose Thompson
f603d21826
Updated my name in multiple locations.
2024-08-21 10:50:39 -07:00
Jacob Pease
938879c5a4
Update PREADY signal to not stall during transmission on reads to read only registers.
2024-08-21 12:39:01 -05:00
Jacob Pease
b7edffdfd4
Removed now inaccurate comments.
2024-08-20 16:38:15 -05:00
Jacob Pease
f960662e93
Removed now inaccurate comments.
2024-08-20 16:38:15 -05:00
Jacob Pease
d8b75440b6
With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
2024-08-20 16:24:37 -05:00
Jacob Pease
baad4e0fd2
With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
2024-08-20 16:24:37 -05:00
Jacob Pease
43b17b5058
Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose.
2024-08-20 14:40:50 -05:00
Jacob Pease
9ac889e3e8
Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose.
2024-08-20 14:40:50 -05:00
David Harris
8e62c578ea
Detect illegal writes to URO HPM counters
2024-08-15 10:43:20 -07:00
David Harris
e5d262063f
Detect illegal writes to URO HPM counters
2024-08-15 10:43:20 -07:00
David Harris
f0f0e96eee
Fixes mstatus.FS to also be set when a FP operation sets a floating-point flag even if it doesnt write a FP register
2024-08-13 07:34:58 -07:00
David Harris
125884eb74
Fixes mstatus.FS to also be set when a FP operation sets a floating-point flag even if it doesnt write a FP register
2024-08-13 07:34:58 -07:00
David Harris
ca82a63de6
Fixed c.slli hint discovered by Lee (Issue 910)
2024-08-13 06:45:45 -07:00
David Harris
705ee60618
Fixed c.slli hint discovered by Lee (Issue 910)
2024-08-13 06:45:45 -07:00
David Harris
64709bccab
Fixed fldsp decompress with rd = 0
2024-08-08 21:45:57 -07:00
David Harris
b334dc50a4
Fixed fldsp decompress with rd = 0
2024-08-08 21:45:57 -07:00
David Harris
010038ec32
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
David Harris
fa98ae8c30
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
Rose Thompson
7164841f83
Added padding into the hw rvvi format.
2024-08-06 18:34:46 -05:00
Jacob Pease
f8f16d2d34
Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv
2024-08-06 17:36:42 -05:00
Jacob Pease
2dc7e0f76f
Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv
2024-08-06 17:36:42 -05:00
Jacob Pease
11ca2567b8
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
af2344d2d5
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
bd07a60c07
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
11a057b0b3
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
