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https://github.com/openhwgroup/cvw
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Renamed aes blocks based on size
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@ -34,8 +34,8 @@ module aes32d(
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logic [7:0] SboxOut;
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logic [31:0] so, mixed;
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aesinvsbox inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
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aesinvsbox8 inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
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assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
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aesinvmixcolumns mix(so, mixed); // Run so through the mixword AES function
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aesinvmixcolumns32 mix(so, mixed); // Run so through the mixword AES function
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mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
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endmodule
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@ -34,8 +34,8 @@ module aes32e(
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logic [7:0] SboxOut;
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logic [31:0] so, mixed;
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aessbox sbox(SboxIn, SboxOut); // Substitute
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aessbox8 sbox(SboxIn, SboxOut); // Substitute
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assign so = {24'h0, SboxOut}; // Pad sbox output
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aesmixcolumns mwd(so, mixed); // Mix Word using aesmixword component
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aesmixcolumns32 mwd(so, mixed); // Mix Word using aesmixword component
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mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
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endmodule
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@ -32,20 +32,19 @@ module aes64d(
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output logic [63:0] result
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);
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logic [127:0] ShiftRowOut;
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logic [63:0] SboxOut, MixcolIn, MixcolOut;
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logic [63:0] ShiftRowOut, SboxOut, MixcolIn, MixcolOut;
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// Apply inverse shiftrows to rs2 and rs1
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aesinvshiftrow srow({rs2, rs1}, ShiftRowOut);
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aesinvshiftrow64 srow({rs2, rs1}, ShiftRowOut);
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// Apply full word inverse substitution to lower doubleord of shiftrow out
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aesinvsbox64 invsbox(ShiftRowOut[63:0], SboxOut);
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aesinvsbox64 invsbox(ShiftRowOut, SboxOut);
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mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn);
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// Apply inverse mixword to sbox outputs
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aesinvmixcolumns invmw0(MixcolIn[31:0], MixcolOut[31:0]);
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aesinvmixcolumns invmw1(MixcolIn[63:32], MixcolOut[63:32]);
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aesinvmixcolumns32 invmw0(MixcolIn[31:0], MixcolOut[31:0]);
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aesinvmixcolumns32 invmw1(MixcolIn[63:32], MixcolOut[63:32]);
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// Final round skips mixcolumns.
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mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
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@ -34,11 +34,10 @@ module aes64e(
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output logic [63:0] result
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);
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logic [127:0] ShiftRowOut;
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logic [63:0] SboxOut, MixcolOut;
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logic [63:0] ShiftRowOut, SboxOut, MixcolOut;
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// AES shiftrow unit
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aesshiftrow srow({rs2,rs1}, ShiftRowOut);
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aesshiftrow64 srow({rs2,rs1}, ShiftRowOut);
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// Apply substitution box to 2 lower words
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// Use the shared sbox in zknde64.sv for the first sbox
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@ -48,8 +47,8 @@ module aes64e(
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aessbox32 sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox
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// Apply mix columns operations
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aesmixcolumns mw0(SboxOut[31:0], MixcolOut[31:0]);
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aesmixcolumns mw1(SboxOut[63:32], MixcolOut[63:32]);
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aesmixcolumns32 mw0(SboxOut[31:0], MixcolOut[31:0]);
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aesmixcolumns32 mw1(SboxOut[63:32], MixcolOut[63:32]);
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// Skip mixcolumns on last round
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mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// aesinvmixcolumns.sv
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// aesinvmixcolumns32.sv
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//
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// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
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// Created: 05 March 2024
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aesinvmixcolumns(
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module aesinvmixcolumns32(
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input logic [31:0] a,
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output logic [31:0] y
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);
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@ -41,8 +41,8 @@ module aesinvmixcolumns(
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assign xor2 = {temp, 3'b0} ^ {1'b0, a1^a3, 2'b0} ^ {2'b0, a1^a0, 1'b0} ^ {3'b0, temp} ^ {3'b0, a1};
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assign xor3 = {temp, 3'b0} ^ {1'b0, a0^a2, 2'b0} ^ {2'b0, a0^a3, 1'b0} ^ {3'b0, temp} ^ {3'b0, a0};
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galoismultinverse gm0 (xor0, y[7:0]);
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galoismultinverse gm1 (xor1, y[15:8]);
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galoismultinverse gm2 (xor2, y[23:16]);
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galoismultinverse gm3 (xor3, y[31:24]);
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galoismultinverse8 gm0 (xor0, y[7:0]);
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galoismultinverse8 gm1 (xor1, y[15:8]);
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galoismultinverse8 gm2 (xor2, y[23:16]);
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galoismultinverse8 gm3 (xor3, y[31:24]);
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endmodule
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@ -31,12 +31,12 @@ module aesinvsbox64(
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);
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// inverse substitutions boxes for each byte of the 32-bit word
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aesinvsbox sbox0(a[7:0], y[7:0]);
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aesinvsbox sbox1(a[15:8], y[15:8]);
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aesinvsbox sbox2(a[23:16], y[23:16]);
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aesinvsbox sbox3(a[31:24], y[31:24]);
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aesinvsbox sbox4(a[39:32], y[39:32]);
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aesinvsbox sbox5(a[47:40], y[47:40]);
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aesinvsbox sbox6(a[55:48], y[55:48]);
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aesinvsbox sbox7(a[63:56], y[63:56]);
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aesinvsbox8 sbox0(a[7:0], y[7:0]);
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aesinvsbox8 sbox1(a[15:8], y[15:8]);
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aesinvsbox8 sbox2(a[23:16], y[23:16]);
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aesinvsbox8 sbox3(a[31:24], y[31:24]);
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aesinvsbox8 sbox4(a[39:32], y[39:32]);
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aesinvsbox8 sbox5(a[47:40], y[47:40]);
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aesinvsbox8 sbox6(a[55:48], y[55:48]);
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aesinvsbox8 sbox7(a[63:56], y[63:56]);
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// aesinvsbox.sv
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// aesinvsbox8.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aesinvsbox(
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module aesinvsbox8(
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input logic [7:0] a,
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output logic [7:0] y
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);
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@ -25,13 +25,11 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aesinvshiftrow(
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module aesinvshiftrow64(
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input logic [127:0] a,
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output logic [127:0] y
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output logic [63:0] y
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);
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assign y = {a[31:24], a[55:48], a[79:72], a[103:96],
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a[127:120], a[23:16], a[47:40], a[71:64],
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a[95:88], a[119:112], a[15:8], a[39:32],
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assign y = {a[95:88], a[119:112], a[15:8], a[39:32],
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a[63:56], a[87:80], a[111:104], a[7:0]};
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// aesmixcolumns.sv
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// aesmixcolumns32.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
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// Created: 20 February 2024
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@ -26,7 +26,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aesmixcolumns(
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module aesmixcolumns32(
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input logic [31:0] a,
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output logic [31:0] y
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);
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@ -36,10 +36,10 @@ module aesmixcolumns(
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assign {a0, a1, a2, a3} = a;
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assign temp = a0 ^ a1 ^ a2 ^ a3;
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galoismultforward gm0 (a0^a1, t0);
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galoismultforward gm1 (a1^a2, t1);
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galoismultforward gm2 (a2^a3, t2);
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galoismultforward gm3 (a3^a0, t3);
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galoismultforward8 gm0 (a0^a1, t0);
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galoismultforward8 gm1 (a1^a2, t1);
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galoismultforward8 gm2 (a2^a3, t2);
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galoismultforward8 gm3 (a3^a0, t3);
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assign y0 = a0 ^ temp ^ t3;
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assign y1 = a1 ^ temp ^ t0;
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@ -31,8 +31,8 @@ module aessbox32(
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);
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// substitutions boxes for each byte of the 32-bit word
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aessbox sbox0(a[7:0], y[7:0]);
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aessbox sbox1(a[15:8], y[15:8]);
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aessbox sbox2(a[23:16], y[23:16]);
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aessbox sbox3(a[31:24], y[31:24]);
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aessbox8 sbox0(a[7:0], y[7:0]);
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aessbox8 sbox1(a[15:8], y[15:8]);
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aessbox8 sbox2(a[23:16], y[23:16]);
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aessbox8 sbox3(a[31:24], y[31:24]);
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// aessbox.sv
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// aessbox8.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aessbox(
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module aessbox8(
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input logic [7:0] a,
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output logic [7:0] y
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);
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@ -25,13 +25,11 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aesshiftrow(
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module aesshiftrow64(
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input logic [127:0] a,
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output logic [127:0] y
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output logic [63:0] y
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);
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assign y = {a[95:88], a[55:48], a[15:8], a[103:96],
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a[63:56], a[23:16], a[111:104], a[71:64],
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a[31:24], a[119:112], a[79:72], a[39:32],
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assign y = {a[31:24], a[119:112], a[79:72], a[39:32],
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a[127:120], a[87:80], a[47:40], a[7:0]};
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endmodule
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module galoismultforward(
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module galoismultforward8(
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input logic [7:0] a,
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output logic [7:0] y
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);
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module galoismultinverse(
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module galoismultinverse8(
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input logic [10:0] a,
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output logic [7:0] y
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);
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