Renamed aes blocks based on size

This commit is contained in:
David Harris 2024-03-16 07:12:36 -07:00
parent c01e4495b1
commit fedd23a3c0
14 changed files with 49 additions and 55 deletions

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@ -34,8 +34,8 @@ module aes32d(
logic [7:0] SboxOut;
logic [31:0] so, mixed;
aesinvsbox inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
aesinvsbox8 inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
aesinvmixcolumns mix(so, mixed); // Run so through the mixword AES function
aesinvmixcolumns32 mix(so, mixed); // Run so through the mixword AES function
mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
endmodule

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@ -34,8 +34,8 @@ module aes32e(
logic [7:0] SboxOut;
logic [31:0] so, mixed;
aessbox sbox(SboxIn, SboxOut); // Substitute
aessbox8 sbox(SboxIn, SboxOut); // Substitute
assign so = {24'h0, SboxOut}; // Pad sbox output
aesmixcolumns mwd(so, mixed); // Mix Word using aesmixword component
aesmixcolumns32 mwd(so, mixed); // Mix Word using aesmixword component
mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
endmodule

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@ -32,20 +32,19 @@ module aes64d(
output logic [63:0] result
);
logic [127:0] ShiftRowOut;
logic [63:0] SboxOut, MixcolIn, MixcolOut;
logic [63:0] ShiftRowOut, SboxOut, MixcolIn, MixcolOut;
// Apply inverse shiftrows to rs2 and rs1
aesinvshiftrow srow({rs2, rs1}, ShiftRowOut);
aesinvshiftrow64 srow({rs2, rs1}, ShiftRowOut);
// Apply full word inverse substitution to lower doubleord of shiftrow out
aesinvsbox64 invsbox(ShiftRowOut[63:0], SboxOut);
aesinvsbox64 invsbox(ShiftRowOut, SboxOut);
mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn);
// Apply inverse mixword to sbox outputs
aesinvmixcolumns invmw0(MixcolIn[31:0], MixcolOut[31:0]);
aesinvmixcolumns invmw1(MixcolIn[63:32], MixcolOut[63:32]);
aesinvmixcolumns32 invmw0(MixcolIn[31:0], MixcolOut[31:0]);
aesinvmixcolumns32 invmw1(MixcolIn[63:32], MixcolOut[63:32]);
// Final round skips mixcolumns.
mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);

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@ -34,11 +34,10 @@ module aes64e(
output logic [63:0] result
);
logic [127:0] ShiftRowOut;
logic [63:0] SboxOut, MixcolOut;
logic [63:0] ShiftRowOut, SboxOut, MixcolOut;
// AES shiftrow unit
aesshiftrow srow({rs2,rs1}, ShiftRowOut);
aesshiftrow64 srow({rs2,rs1}, ShiftRowOut);
// Apply substitution box to 2 lower words
// Use the shared sbox in zknde64.sv for the first sbox
@ -48,8 +47,8 @@ module aes64e(
aessbox32 sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox
// Apply mix columns operations
aesmixcolumns mw0(SboxOut[31:0], MixcolOut[31:0]);
aesmixcolumns mw1(SboxOut[63:32], MixcolOut[63:32]);
aesmixcolumns32 mw0(SboxOut[31:0], MixcolOut[31:0]);
aesmixcolumns32 mw1(SboxOut[63:32], MixcolOut[63:32]);
// Skip mixcolumns on last round
mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);

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@ -1,5 +1,5 @@
///////////////////////////////////////////
// aesinvmixcolumns.sv
// aesinvmixcolumns32.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 05 March 2024
@ -25,7 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvmixcolumns(
module aesinvmixcolumns32(
input logic [31:0] a,
output logic [31:0] y
);
@ -41,8 +41,8 @@ module aesinvmixcolumns(
assign xor2 = {temp, 3'b0} ^ {1'b0, a1^a3, 2'b0} ^ {2'b0, a1^a0, 1'b0} ^ {3'b0, temp} ^ {3'b0, a1};
assign xor3 = {temp, 3'b0} ^ {1'b0, a0^a2, 2'b0} ^ {2'b0, a0^a3, 1'b0} ^ {3'b0, temp} ^ {3'b0, a0};
galoismultinverse gm0 (xor0, y[7:0]);
galoismultinverse gm1 (xor1, y[15:8]);
galoismultinverse gm2 (xor2, y[23:16]);
galoismultinverse gm3 (xor3, y[31:24]);
galoismultinverse8 gm0 (xor0, y[7:0]);
galoismultinverse8 gm1 (xor1, y[15:8]);
galoismultinverse8 gm2 (xor2, y[23:16]);
galoismultinverse8 gm3 (xor3, y[31:24]);
endmodule

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@ -31,12 +31,12 @@ module aesinvsbox64(
);
// inverse substitutions boxes for each byte of the 32-bit word
aesinvsbox sbox0(a[7:0], y[7:0]);
aesinvsbox sbox1(a[15:8], y[15:8]);
aesinvsbox sbox2(a[23:16], y[23:16]);
aesinvsbox sbox3(a[31:24], y[31:24]);
aesinvsbox sbox4(a[39:32], y[39:32]);
aesinvsbox sbox5(a[47:40], y[47:40]);
aesinvsbox sbox6(a[55:48], y[55:48]);
aesinvsbox sbox7(a[63:56], y[63:56]);
aesinvsbox8 sbox0(a[7:0], y[7:0]);
aesinvsbox8 sbox1(a[15:8], y[15:8]);
aesinvsbox8 sbox2(a[23:16], y[23:16]);
aesinvsbox8 sbox3(a[31:24], y[31:24]);
aesinvsbox8 sbox4(a[39:32], y[39:32]);
aesinvsbox8 sbox5(a[47:40], y[47:40]);
aesinvsbox8 sbox6(a[55:48], y[55:48]);
aesinvsbox8 sbox7(a[63:56], y[63:56]);
endmodule

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@ -1,5 +1,5 @@
///////////////////////////////////////////
// aesinvsbox.sv
// aesinvsbox8.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
@ -25,7 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvsbox(
module aesinvsbox8(
input logic [7:0] a,
output logic [7:0] y
);

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@ -25,13 +25,11 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvshiftrow(
module aesinvshiftrow64(
input logic [127:0] a,
output logic [127:0] y
output logic [63:0] y
);
assign y = {a[31:24], a[55:48], a[79:72], a[103:96],
a[127:120], a[23:16], a[47:40], a[71:64],
a[95:88], a[119:112], a[15:8], a[39:32],
assign y = {a[95:88], a[119:112], a[15:8], a[39:32],
a[63:56], a[87:80], a[111:104], a[7:0]};
endmodule

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@ -1,5 +1,5 @@
///////////////////////////////////////////
// aesmixcolumns.sv
// aesmixcolumns32.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
// Created: 20 February 2024
@ -26,7 +26,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module aesmixcolumns(
module aesmixcolumns32(
input logic [31:0] a,
output logic [31:0] y
);
@ -36,10 +36,10 @@ module aesmixcolumns(
assign {a0, a1, a2, a3} = a;
assign temp = a0 ^ a1 ^ a2 ^ a3;
galoismultforward gm0 (a0^a1, t0);
galoismultforward gm1 (a1^a2, t1);
galoismultforward gm2 (a2^a3, t2);
galoismultforward gm3 (a3^a0, t3);
galoismultforward8 gm0 (a0^a1, t0);
galoismultforward8 gm1 (a1^a2, t1);
galoismultforward8 gm2 (a2^a3, t2);
galoismultforward8 gm3 (a3^a0, t3);
assign y0 = a0 ^ temp ^ t3;
assign y1 = a1 ^ temp ^ t0;

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@ -31,8 +31,8 @@ module aessbox32(
);
// substitutions boxes for each byte of the 32-bit word
aessbox sbox0(a[7:0], y[7:0]);
aessbox sbox1(a[15:8], y[15:8]);
aessbox sbox2(a[23:16], y[23:16]);
aessbox sbox3(a[31:24], y[31:24]);
aessbox8 sbox0(a[7:0], y[7:0]);
aessbox8 sbox1(a[15:8], y[15:8]);
aessbox8 sbox2(a[23:16], y[23:16]);
aessbox8 sbox3(a[31:24], y[31:24]);
endmodule

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@ -1,5 +1,5 @@
///////////////////////////////////////////
// aessbox.sv
// aessbox8.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
@ -25,7 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aessbox(
module aessbox8(
input logic [7:0] a,
output logic [7:0] y
);

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@ -25,13 +25,11 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesshiftrow(
module aesshiftrow64(
input logic [127:0] a,
output logic [127:0] y
output logic [63:0] y
);
assign y = {a[95:88], a[55:48], a[15:8], a[103:96],
a[63:56], a[23:16], a[111:104], a[71:64],
a[31:24], a[119:112], a[79:72], a[39:32],
assign y = {a[31:24], a[119:112], a[79:72], a[39:32],
a[127:120], a[87:80], a[47:40], a[7:0]};
endmodule

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@ -25,7 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module galoismultforward(
module galoismultforward8(
input logic [7:0] a,
output logic [7:0] y
);

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@ -25,7 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module galoismultinverse(
module galoismultinverse8(
input logic [10:0] a,
output logic [7:0] y
);