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Beginning subword cleanup.

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This commit is contained in:
Rose Thompson 2024-02-22 09:37:16 -06:00
parent 1ece6f8eae
commit 7e1ea1e6d9
2 changed files with 7 additions and 16 deletions
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2
src/lsu/lsu.sv
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@ -425,7 +425,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////////////////////
if(MISALIGN_SUPPORT) begin
subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
subwordreadmisaligned #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM);
end else begin

21
src/lsu/subworddreadmisaligned.sv
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@ -40,10 +40,11 @@ module subwordreadmisaligned #(parameter LLEN)
logic [7:0] ByteM;
logic [15:0] HalfwordM;
logic [31:0] WordM;
logic [4:0] PAdrSwap;
logic [4:0] BigEndianPAdr;
logic [4:0] LengthM;
// Funct3M[2] is the unsigned bit. mask upper bits.
// Funct3M[1:0] is the size of the memory access.
assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
@ -66,14 +67,14 @@ module subwordreadmisaligned #(parameter LLEN)
logic [LLEN*2-1:0] ReadDataAlignedM;
assign ReadDataAlignedM = ReadDataWordMuxM >> (PAdrSwap[$clog2(LLEN/4)-1:0] * 8);
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
if (LLEN == 128) begin:swrmux
logic [31:0] WordM;
logic [63:0] DblWordM;
logic [127:0] QdWordM;
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
assign DblWordM = ReadDataAlignedM[63:0];
assign QdWordM =ReadDataAlignedM[127:0];
@ -92,12 +93,8 @@ module subwordreadmisaligned #(parameter LLEN)
endcase
end else if (LLEN == 64) begin:swrmux
logic [31:0] WordM;
logic [63:0] DblWordM;
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
assign DblWordM = ReadDataAlignedM[63:0];
// sign extension/ NaN boxing
@ -116,12 +113,6 @@ module subwordreadmisaligned #(parameter LLEN)
end else begin:swrmux // 32-bit
logic [31:0] WordM;
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
// sign extension
always_comb
case(Funct3M)