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https://github.com/openhwgroup/cvw
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update aes_instructions
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ac9068d22c
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@ -39,16 +39,21 @@ module aes32dsi(input logic [1:0] bs,
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logic [31:0] so_rotate;
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// shamt = bs * 8
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assign shamt = {bs, 3'b0};
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assign shamt = {bs, 3'b0};
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// Shift rs2 right by shamt and take the lower byte
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assign sbox_in_32 = (rs2 >> shamt);
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assign sbox_in = sbox_in_32[7:0];
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assign sbox_in = sbox_in_32[7:0];
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// Apply inverse sbox to si
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aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out));
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aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out));
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// Pad output of inverse substitution box
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assign so = {24'h000000,sbox_out};
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assign so = {24'h000000,sbox_out};
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// Rotate the substitution box output left by shamt (bs * 8)
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rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate));
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rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate));
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// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
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assign data_out = rs1 ^ so_rotate;
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@ -40,18 +40,24 @@ module aes32dsmi(input logic [1:0] bs,
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logic [31:0] mixed_rotate;
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// shamt = bs * 8
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assign shamt = {bs, 3'b0};
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assign shamt = {bs, 3'b0};
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// Shift rs2 right by shamt and take the lower byte
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assign sbox_in_32 = (rs2 >> shamt);
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assign sbox_in = sbox_in_32[7:0];
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assign sbox_in = sbox_in_32[7:0];
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// Apply inverse sbox to si
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aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out));
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aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out));
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// Pad output of inverse substitution box
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assign so = {24'h000000,sbox_out};
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assign so = {24'h000000,sbox_out};
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// Run so through the mixword AES function
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inv_mixword mix(.word(so),.mixed_word(mixed));
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inv_mixword mix(.word(so),.mixed_word(mixed));
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// Rotate the substitution box output left by shamt (bs * 8)
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rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate));
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rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate));
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// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
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assign data_out = rs1 ^ mixed_rotate;
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@ -36,9 +36,11 @@ module aes64ds(input logic [63:0] rs1,
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// Apply inverse shiftrows to rs2 and rs1
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aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out));
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// Apply full word inverse substitution to lower 2 words of shiftrow out
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aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0));
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aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1));
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// Concatenate the two substitution outputs to get result
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assign data_out = {sbox_out_1, sbox_out_0};
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@ -37,17 +37,17 @@ module aes64dsm(input logic [63:0] rs1,
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logic [31:0] mixcol_out_1;
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// Apply inverse shiftrows to rs2 and rs1
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aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out));
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aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out));
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// Apply full word inverse substitution to lower 2 words of shiftrow out
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aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0));
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aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1));
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aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1));
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// Apply inverse mixword to sbox outputs
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inv_mixword inv_mw_0(.word(sbox_out_0),.mixed_word(mixcol_out_0));
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inv_mixword inv_mw_1(.word(sbox_out_1),.mixed_word(mixcol_out_1));
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inv_mixword inv_mw_1(.word(sbox_out_1),.mixed_word(mixcol_out_1));
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// Concatenate mixed words for output
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assign data_out = {mixcol_out_1,mixcol_out_0};
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endmodule
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@ -33,7 +33,8 @@ module aes64es(input logic [63:0] rs1,
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logic [127:0] shiftRow_out;
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// AES shiftrow unit
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aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out));
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aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out));
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// Apply substitution box to 2 lower words
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aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(data_out[31:0]));
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aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(data_out[63:32]));
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@ -34,14 +34,14 @@ module aes64esm(input logic [63:0] rs1,
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logic [63:0] sbox_out;
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// AES shiftrow unit
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aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out));
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aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out));
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// Apply substitution box to 2 lower words
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aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out[31:0]));
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aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out[63:32]));
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aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out[63:32]));
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// Apply mix columns operations
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mixword mw0(.word(sbox_out[31:0]),.mixed_word(data_out[31:0]));
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mixword mw1(.word(sbox_out[63:32]),.mixed_word(data_out[63:32]));
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endmodule
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@ -28,7 +28,7 @@
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module aes64im(input logic [63:0] rs1,
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output logic [63:0] data_out);
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inv_mixword inv_mw_0(.word(rs1[31:0]),.mixed_word(data_out[31:0]));
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inv_mixword inv_mw_1(.word(rs1[63:32]),.mixed_word(data_out[63:32]));
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inv_mixword inv_mw_0(.word(rs1[31:0]),.mixed_word(data_out[31:0]));
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inv_mixword inv_mw_1(.word(rs1[63:32]),.mixed_word(data_out[63:32]));
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endmodule
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49
src/ieu/aes_instructions/rcon_lut_128.sv
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49
src/ieu/aes_instructions/rcon_lut_128.sv
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@ -0,0 +1,49 @@
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///////////////////////////////////////////
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// rcon_lut_128.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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//
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// Purpose: aes64ks1i instruction
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rcon_lut_128(input logic [3:0] RD,
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output logic [7:0] rcon_out);
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always_comb
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begin
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case(RD)
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4'h0 : rcon_out = 8'h01;
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4'h1 : rcon_out = 8'h02;
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4'h2 : rcon_out = 8'h04;
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4'h3 : rcon_out = 8'h08;
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4'h4 : rcon_out = 8'h10;
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4'h5 : rcon_out = 8'h20;
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4'h6 : rcon_out = 8'h40;
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4'h7 : rcon_out = 8'h80;
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4'h8 : rcon_out = 8'h1b;
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4'h9 : rcon_out = 8'h36;
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4'hA : rcon_out = 8'h00;
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default : rcon_out = 8'h00;
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endcase
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end
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endmodule
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64
src/ieu/aes_instructions/rrot8.sv
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64
src/ieu/aes_instructions/rrot8.sv
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@ -0,0 +1,64 @@
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///////////////////////////////////////////
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// rrot8.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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//
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// Purpose: aes64ks1i instruction
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rrot8(input logic[31:0] x,
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output logic [31:0] result);
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assign result[0] = x[8];
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assign result[1] = x[9];
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assign result[2] = x[10];
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assign result[3] = x[11];
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assign result[4] = x[12];
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assign result[5] = x[13];
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assign result[6] = x[14];
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assign result[7] = x[15];
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assign result[8] = x[16];
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assign result[9] = x[17];
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assign result[10] = x[18];
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assign result[11] = x[19];
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assign result[12] = x[20];
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assign result[13] = x[21];
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assign result[14] = x[22];
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assign result[15] = x[23];
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assign result[16] = x[24];
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assign result[17] = x[25];
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assign result[18] = x[26];
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assign result[19] = x[27];
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assign result[20] = x[28];
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assign result[21] = x[29];
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assign result[22] = x[30];
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assign result[23] = x[31];
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assign result[24] = x[0];
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assign result[25] = x[1];
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assign result[26] = x[2];
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assign result[27] = x[3];
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assign result[28] = x[4];
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assign result[29] = x[5];
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assign result[30] = x[6];
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assign result[31] = x[7];
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endmodule
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