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Shared middle and final round aes32 to cut size 50%

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This commit is contained in:
David Harris 2024-03-10 23:40:12 -07:00
parent f72e5048de
commit f950067600
5 changed files with 25 additions and 111 deletions
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16
src/ieu/aes_instructions/aes32dsmi.sv → src/ieu/aes_instructions/aes32d.sv
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@ -1,10 +1,10 @@
///////////////////////////////////////////
// aes32dsmi.sv
// aes32d.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes32dsmi instruction: RV32 middle round AES decryption
// Purpose: aes32dsmi and aes32dsi instruction: RV32 middle and final round AES decryption
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
@ -25,22 +25,24 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes32dsmi(
module aes32d(
input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
input logic finalround,
output logic [31:0] result
);
logic [4:0] shamt;
logic [7:0] SboxIn, SboxOut;
logic [31:0] so, mixed, mixedrotate;
logic [31:0] so, mixed, rotin, rotout;
assign shamt = {bs, 3'b0}; // shamt = bs * 8 (convert bytes to bits)
assign SboxIn = rs2[shamt +: 8]; // select byte bs of rs2
aesinvsbox inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
aesinvmixcolumns mix(so, mixed); // Run so through the mixword AES function
rotate mrot(mixed, shamt, mixedrotate); // Rotate the mixcolumns output left by shamt (bs * 8)
assign DataOut = rs1 ^ mixedrotate; // xor with running value
mux2 #(32) rmux(mixed, so, finalround, rotin); // on final round, rotate so rather than mixed
rotate #(32) rot(rotin, shamt, rotout); // Rotate left by shamt (bs * 8)
assign result = rs1 ^ rotout; // xor with running value
endmodule

45
src/ieu/aes_instructions/aes32dsi.sv
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@ -1,45 +0,0 @@
///////////////////////////////////////////
// aes32dsi.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes32dsi instruction: RV32 final round AES decryption
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes32dsi(
input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
);
logic [4:0] shamt;
logic [7:0] SboxIn, SboxOut;
logic [31:0] so, sorotate;
assign shamt = {bs, 3'b0}; // shamt = bs * 8 (convert bytes to bits)
assign SboxIn = rs2[shamt +: 8]; // select byte bs of rs2
aesinvsbox inv_sbox(SboxIn, SboxOut); // Apply inverse sbox
assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
rotate sorot(so, shamt, sorotate); // Rotate the substitution box output left by shamt (bs * 8)
assign DataOut = rs1 ^ sorotate; // xor with running value
endmodule

26
src/ieu/aes_instructions/aes32esmi.sv → src/ieu/aes_instructions/aes32e.sv
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@ -1,10 +1,10 @@
///////////////////////////////////////////
// aes32esmi.sv
// aes32e.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes32esmi instruction: RV32 middle round AES encryption
// Purpose: aes32esmi and aes32esi instruction: RV32 middle and final round AES encryption
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
@ -25,22 +25,24 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes32esmi(
module aes32e(
input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
input logic finalround,
output logic [31:0] result
);
logic [4:0] shamt;
logic [7:0] SboxIn, SboxOut;
logic [31:0] so, mixed, mixedrotate;
logic [31:0] so, mixed, rotin, rotout;
assign shamt = {bs, 3'b0}; // shamt = bs * 8 (convert bytes to bits)
assign SboxIn = rs2[shamt +: 8]; // select byte bs of rs2
aessbox sbox(SboxIn, SboxOut); // Substitute
assign so = {24'h0, SboxOut}; // Pad sbox output
aesmixcolumns mwd(so, mixed); // Mix Word using aesmixword component
rotate mrot(mixed, shamt, mixedrotate); // Rotate the mixcolumns output left by shamt (bs * 8)
assign DataOut = rs1 ^ mixedrotate; // xor with running value
assign shamt = {bs, 3'b0}; // shamt = bs * 8 (convert bytes to bits)
assign SboxIn = rs2[shamt +: 8]; // select byte bs of rs2
aessbox sbox(SboxIn, SboxOut); // Substitute
assign so = {24'h0, SboxOut}; // Pad sbox output
aesmixcolumns mwd(so, mixed); // Mix Word using aesmixword component
mux2 #(32) rmux(mixed, so, finalround, rotin); // on final round, rotate so rather than mixed
rotate #(32) mrot(rotin, shamt, rotout); // Rotate the mixcolumns output left by shamt (bs * 8)
assign result = rs1 ^ rotout; // xor with running value
endmodule

45
src/ieu/aes_instructions/aes32esi.sv
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@ -1,45 +0,0 @@
///////////////////////////////////////////
// aes32esi.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes32esi instruction: : RV32 final round AES encryption
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes32esi(
input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
);
logic [4:0] shamt;
logic [7:0] SboxIn, SboxOut;
logic [31:0] so, sorotate;
assign shamt = {bs, 3'b0}; // shamt = bs * 8 (convert bytes to bits)
assign SboxIn = rs2[shamt +: 8]; // select byte bs of rs2
aessbox subbox(SboxIn, SboxOut); // Substitute
assign so = {24'h0, SboxOut}; // Pad sbox output
rotate sorot(so, shamt, sorotate); // Rotate the substitution box output left by shamt (bs * 8)
assign DataOut = rs1 ^ sorotate; // xor with running value
endmodule

4
src/ieu/bmu/bitmanipalu.sv
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@ -114,13 +114,13 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
// ZKND Unit
if (P.ZKND_SUPPORTED) begin: zknd
if (P.XLEN == 32) zknd32 #(P.XLEN) ZKND32(.A(ABMU), .B(BBMU), .Funct7, .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult);
if (P.XLEN == 32) aes32d aes32d(.bs(Funct7[6:5]), .rs1(ABMU), .rs2(BBMU), .finalround(~ZBBSelect[0]), .result(ZKNDResult));
else zknd64 #(P.XLEN) ZKND64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult);
end else assign ZKNDResult = 0;
// ZKNE Unit
if (P.ZKNE_SUPPORTED) begin: zkne
if (P.XLEN == 32) zkne32 #(P.XLEN) ZKNE32(.A(ABMU), .B(BBMU), .Funct7, .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult);
if (P.XLEN == 32) aes32e aes32e(.bs(Funct7[6:5]), .rs1(ABMU), .rs2(BBMU), .finalround(~ZBBSelect[0]), .result(ZKNEResult));
else zkne64 #(P.XLEN) ZKNE64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult);
end else assign ZKNEResult = 0;