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https://github.com/openhwgroup/cvw
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Shared AND gate in ALU for extract / and paths
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@ -50,6 +50,7 @@ module alu import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] CondMaskB; // Result of B mask select mux
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logic [P.XLEN-1:0] CondShiftA; // Result of A shifted select mux
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logic [P.XLEN-1:0] ZeroCondMaskInvB; // B input to AND gate, accounting for czero.* instructions
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logic [P.XLEN-1:0] AndResult; // AND result
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logic Carry, Neg; // Flags: carry out, negative
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logic LT, LTU; // Less than, Less than unsigned
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logic Asign, Bsign; // Sign bits of A, B
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@ -72,6 +73,7 @@ module alu import cvw::*; #(parameter cvw_t P) (
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assign Bsign = B[P.XLEN-1];
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assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg;
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assign LTU = ~Carry;
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assign AndResult = A & ZeroCondMaskInvB;
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// Select appropriate ALU Result
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always_comb
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@ -81,9 +83,10 @@ module alu import cvw::*; #(parameter cvw_t P) (
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3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT}; // slt
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3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU}; // sltu
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3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv
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3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
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// 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskInvB)}} : Shift; // bext (or IEU shift when BMU not supported)
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3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(AndResult)}} : Shift; // bext (or IEU shift when BMU not supported)
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3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
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3'b111: FullResult = A & ZeroCondMaskInvB; // and, bclr, czero.*
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3'b111: FullResult = AndResult; // and, bclr, czero.*
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endcase
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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