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AES cleanup
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@ -32,7 +32,7 @@ module aes64d(
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output logic [63:0] result
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);
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logic [63:0] ShiftRowsOut, SboxOut, MixcolIn, MixcolOut;
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logic [63:0] ShiftRowsOut, SboxOut, MixcolsIn, MixcolsOut;
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// Apply inverse shiftrows to rs2 and rs1
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aesinvshiftrows64 srow({rs2, rs1}, ShiftRowsOut);
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@ -40,12 +40,12 @@ module aes64d(
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// Apply full word inverse substitution to lower doubleord of shiftrow out
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aesinvsbox64 invsbox(ShiftRowsOut, SboxOut);
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mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn);
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mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolsIn);
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// Apply inverse MixColumns to sbox outputs
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aesinvmixcolumns32 invmw0(MixcolIn[31:0], MixcolOut[31:0]);
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aesinvmixcolumns32 invmw1(MixcolIn[63:32], MixcolOut[63:32]);
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aesinvmixcolumns32 invmw0(MixcolsIn[31:0], MixcolsOut[31:0]);
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aesinvmixcolumns32 invmw1(MixcolsIn[63:32], MixcolsOut[63:32]);
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// Final round skips mixcolumns.
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mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
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mux2 #(64) resultmux(MixcolsOut, SboxOut, finalround, result);
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endmodule
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@ -34,7 +34,7 @@ module aes64e(
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output logic [63:0] result
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);
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logic [63:0] ShiftRowsOut, SboxOut, MixcolOut;
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logic [63:0] ShiftRowsOut, SboxOut, MixcolsOut;
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// AES shiftrow unit
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aesshiftrows64 srow({rs2,rs1}, ShiftRowsOut);
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@ -47,9 +47,9 @@ module aes64e(
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aessbox32 sbox1(ShiftRowsOut[63:32], SboxOut[63:32]); // instantiate second sbox
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// Apply MixColumns operations
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aesmixcolumns32 mw0(SboxOut[31:0], MixcolOut[31:0]);
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aesmixcolumns32 mw1(SboxOut[63:32], MixcolOut[63:32]);
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aesmixcolumns32 mw0(SboxOut[31:0], MixcolsOut[31:0]);
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aesmixcolumns32 mw1(SboxOut[63:32], MixcolsOut[63:32]);
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// Skip mixcolumns on last round
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mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
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mux2 #(64) resultmux(MixcolsOut, SboxOut, finalround, result);
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endmodule
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