Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

More simplifying sha512_32

Browse Source
This commit is contained in:
David Harris 2024-05-23 05:46:56 -07:00
parent d9a1691c83
commit ac153bc4ed
2 changed files with 20 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/ieu/bmu/bmuctrl.sv
View File

@ -264,7 +264,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sig1h
17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sig1l
17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_1_0_0_0_0_0; // sha512sum0r
17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1101_1_0_0_1_0_0_0_0_0; // sha512sum1r
17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1110_1_0_0_1_0_0_0_0_0; // sha512sum1r
endcase
else if (P.XLEN==64)

46
src/ieu/sha/sha512_32.sv
View File

@ -31,45 +31,37 @@ module sha512_32 (
output logic [31:0] result
);
logic [31:0] x[6][3];
logic [31:0] x[4][3];
logic [31:0] y[3];
// sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r} select shifted operands for 32-bit xor6
// sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r} select shifted operands for 32-bit xor
// sha512sig0h
// The l flavors differ from h by using low bits of B instead of zeros in x[0/1][2]
// sha512sig0h/l
assign x[0][0] = {B[0], A[31:1]};
assign x[0][1] = {B[7:0], A[31:8]};
assign x[0][2] = {7'b0, A[31:7]};
assign x[0][2] = {B[6:0] & {7{ZKNHSelect[0]}}, A[31:7]};
// sha512sig0l
assign x[1][0] = x[0][0];
assign x[1][1] = x[0][1];
assign x[1][2] = {B[6:0], A[31:7]};
// sha512sig1h
assign x[2][0] = {A[28:0], B[31:29]};
assign x[2][1] = {B[18:0], A[31:19]};
assign x[2][2] = {6'b0, A[31:6]};
// sha512sig1l
assign x[3][0] = x[2][0];
assign x[3][1] = x[2][1];
assign x[3][2] = {B[5:0], A[31:6]};
// sha512sig1h/l
assign x[1][0] = {A[28:0], B[31:29]};
assign x[1][1] = {B[18:0], A[31:19]};
assign x[1][2] = {B[5:0] & {6{ZKNHSelect[0]}}, A[31:6]};
// sha512sum0r
assign x[4][0] = {A[6:0], B[31:7]};
assign x[4][1] = {A[1:0], B[31:2]};
assign x[4][2] = {B[27:0], A[31:28]};
assign x[2][0] = {A[6:0], B[31:7]};
assign x[2][1] = {A[1:0], B[31:2]};
assign x[2][2] = {B[27:0], A[31:28]};
// sha512sum1r
assign x[5][0] = {A[8:0], B[31:9]};
assign x[5][1] = {B[13:0], A[31:14]};
assign x[5][2] = {B[17:0], A[31:18]};
assign x[3][0] = {A[8:0], B[31:9]};
assign x[3][1] = {B[13:0], A[31:14]};
assign x[3][2] = {B[17:0], A[31:18]};
// 32-bit muxes to select inputs to xor6 for sha512
assign y[0] = x[ZKNHSelect[2:0]][0];
assign y[1] = x[ZKNHSelect[2:0]][1];
assign y[2] = x[ZKNHSelect[2:0]][2];
assign y[0] = x[ZKNHSelect[2:1]][0];
assign y[1] = x[ZKNHSelect[2:1]][1];
assign y[2] = x[ZKNHSelect[2:1]][2];
// sha512 32-bit xor6
assign result = y[0] ^ y[1] ^ y[2];