Tied dangling signals to 0 for some configs to make VCS lint happy

src/ifu/ifu.sv

@@ -286,16 +286,18 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
       assign IFUHBURST = 3'b0;
       assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0;
     end
+
+    // mux between the alignments of uncached reads.
+    if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16], 
+                                                      FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
+                                                      PCSpillF[2:1], ShiftUncachedInstr);
+    else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
   end else begin : nobus // block: bus
-    assign {BusStall, CacheCommittedF} = '0;   
+    assign {IFUHADDR, IFUHWRITE, IFUHSIZE, IFUHBURST, IFUHTRANS, 
+            BusStall, CacheCommittedF, BusCommittedF, FetchBuffer} = '0;   
     assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
     assign InstrRawF = IROMInstrF;
   end
-
-  // mux between the alignments of uncached reads.
-  if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16], FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
-                                                    PCSpillF[2:1], ShiftUncachedInstr);
-  else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
   
   assign IFUCacheBusStallF = ICacheStallF | BusStall;
   assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;

src/lsu/lsu.sv

@@ -383,7 +383,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
     end
   end else begin: nobus // block: bus, only DTIM
-    assign LSUHWDATA = '0; 
+    assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0; 
+    assign DCacheReadDataWordM = '0;
     assign ReadDataWordMuxM = DTIMReadDataWordM;
     assign {BusStall, BusCommittedM} = '0;   
     assign {DCacheMiss, DCacheAccess} = '0;

src/lsu/subwordread.sv

@@ -52,6 +52,7 @@ module subwordread import cvw::*;  #(parameter cvw_t P) (
   // Use indexed part select to imply muxes to select each size of subword
   if (P.LLEN == 128) mux2 #(64) dblmux(ReadDataWordMuxM[63:0], ReadDataWordMuxM[127:64], PAdrSwapM[3], DblWordM);
   else if (P.LLEN == 64) assign DblWordM = ReadDataWordMuxM;
+  else assign DblWordM = '0; // unused for RV32F
   if (P.LLEN >= 64) mux2 #(32) wordmux(DblWordM[31:0], DblWordM[63:32], PAdrSwapM[2], WordM);
   else assign WordM = ReadDataWordMuxM;
   mux2 #(16) halfwordmux(WordM[15:0], WordM[31:16], PAdrSwapM[1], HalfwordM);

src/wally/wallypipelinedcore.sv

@@ -264,6 +264,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .HREADY, .HRESP, .HCLK, .HRESETn,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
       .HPROT, .HTRANS, .HMASTLOCK);
+  end else begin
+    assign {IFUHREADY, LSUHREADY, HCLK, HRESETn, HADDR, HWDATA,
+            HWSTRB, HWRITE, HSIZE, HBURST, HPROT, HTRANS, HMASTLOCK} = '0;
   end
 
   // global stall and flush control  
@@ -302,15 +305,12 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
       .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
   end else begin
-    assign CSRReadValW      = '0;
-    assign EPCM             = '0;
-    assign TrapVectorM      = '0;
-    assign RetM             = 1'b0;
-    assign TrapM            = 1'b0;
-    assign wfiM             = 1'b0;
-    assign IntPendingM      = 1'b0;
-    assign sfencevmaM       = 1'b0;
-    assign BigEndianM       = 1'b0;
+    assign {CSRReadValW, PrivilegeModeW, 
+            SATP_REGW, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_MPP, STATUS_FS, FRM_REGW,
+            // PMPCFG_ARRAY_REGW, PMPADDR_ARRAY_REGW, 
+            ENVCFG_CBE, ENVCFG_PBMTE, ENVCFG_ADUE, 
+            EPCM, TrapVectorM, RetM, TrapM,
+            sfencevmaM, BigEndianM, wfiM, IntPendingM} = '0;
   end
 
   // multiply/divide unit
@@ -351,15 +351,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .SetFflagsM,                         // FPU flags (to privileged unit)
       .FIntDivResultW); 
   end else begin                           // no F_SUPPORTED or D_SUPPORTED; tie outputs low
-    assign FPUStallD        = 1'b0;
-    assign FWriteIntE       = 1'b0; 
-    assign FCvtIntE         = 1'b0;
-    assign FIntResM         = '0;
-    assign FCvtIntW         = 1'b0;
-    assign FDivBusyE        = 1'b0;
-    assign IllegalFPUInstrD = 1'b1;
-    assign SetFflagsM       = '0;
-    assign FpLoadStoreM     = 1'b0;
+    assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, 
+            IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,
+            FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0;
   end
   
 endmodule

src/wally/wallypipelinedsoc.sv

@@ -85,6 +85,9 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
       .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,
       .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, 
       .UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
+  end else begin
+    assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt,
+            MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; 
   end
 
 endmodule