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Crypto formatting cleanup

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This commit is contained in:
David Harris 2024-03-10 20:45:27 -07:00
parent 34058ddbf0
commit e4724b8d0e
14 changed files with 32 additions and 89 deletions
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7
src/ieu/sha_instructions/sha256sig0.sv
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@ -30,11 +30,8 @@ module sha256sig0 #(parameter WIDTH=32) (
output logic [WIDTH-1:0] result
);
logic [31:0] ror7;
logic [31:0] ror18;
logic [31:0] sh3;
logic [31:0] exts;
logic [31:0] ror7, ror18, sh3, exts;
assign ror7 = {rs1[6:0], rs1[31:7]};
assign ror18 = {rs1[17:0], rs1[31:18]};
assign sh3 = {3'b0, rs1[31:3]};

7
src/ieu/sha_instructions/sha256sig1.sv
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@ -30,14 +30,11 @@ module sha256sig1 #(parameter WIDTH=32) (
output logic [WIDTH-1:0] result
);
logic [31:0] ror17;
logic [31:0] ror19;
logic [31:0] sh10;
logic [31:0] exts;
logic [31:0] ror17, ror19, sh10, exts;
assign ror17 = {rs1[16:0], rs1[31:17]};
assign ror19 = {rs1[18:0], rs1[31:19]};
assign sh10 = {10'b0, rs1[31:10]};
assign sh10 = {10'b0, rs1[31:10]};
// Assign output to xor of 3 rotates
assign exts = ror17 ^ ror19 ^ sh10;

9
src/ieu/sha_instructions/sha256sum0.sv
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@ -30,12 +30,9 @@ module sha256sum0 #(parameter WIDTH=32) (
output logic [WIDTH-1:0] result
);
logic [31:0] ror2;
logic [31:0] ror13;
logic [31:0] ror22;
logic [31:0] exts;
assign ror2 = {rs1[1:0], rs1[31:2]};
logic [31:0] ror2, ror13, ror22, exts;
assign ror2 = {rs1[1:0], rs1[31:2]};
assign ror13 = {rs1[12:0], rs1[31:13]};
assign ror22 = {rs1[21:0], rs1[31:22]};

7
src/ieu/sha_instructions/sha256sum1.sv
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@ -30,11 +30,8 @@ module sha256sum1 #(parameter WIDTH=32) (
output logic [WIDTH-1:0] result
);
logic [31:0] ror6;
logic [31:0] ror11;
logic [31:0] ror25;
logic [31:0] exts;
logic [31:0] ror6, ror11, ror25, exts;
assign ror6 = {rs1[5:0], rs1[31:6]};
assign ror11 = {rs1[10:0], rs1[31:11]};
assign ror25 = {rs1[24:0], rs1[31:25]};

6
src/ieu/sha_instructions/sha512sig0.sv
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@ -30,11 +30,9 @@ module sha512sig0(
output logic [63:0] result
);
logic [63:0] ror1;
logic [63:0] ror8;
logic [63:0] sh7;
logic [63:0] ror1, ror8, sh7;
assign ror1 = {rs1[0], rs1[63:1]};
assign ror1 = {rs1[0], rs1[63:1]};
assign ror8 = {rs1[7:0], rs1[63:8]};
assign sh7 = rs1 >> 7;

10
src/ieu/sha_instructions/sha512sig0h.sv
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@ -31,14 +31,8 @@ module sha512sig0h(
output logic [31:0] DataOut
);
// RS1 Shifts
logic [31:0] shift1;
logic [31:0] shift7;
logic [31:0] shift8;
// RS2 Shifts
logic [31:0] shift31;
logic [31:0] shift24;
logic [31:0] shift1, shift7, shift8; // rs1 shifts
logic [31:0] shift31, shift24; // rs2 shifts
// Shift rs1
assign shift1 = rs1 >> 1;

11
src/ieu/sha_instructions/sha512sig0l.sv
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@ -31,15 +31,8 @@ module sha512sig0l(
output logic [31:0] DataOut
);
// rs1 operations
logic [31:0] shift1;
logic [31:0] shift7;
logic [31:0] shift8;
// rs2 operations
logic [31:0] shift31;
logic [31:0] shift25;
logic [31:0] shift24;
logic [31:0] shift1, shift7, shift8; // rs1 shifts
logic [31:0] shift31, shift25, shift24; // rs2 shifts
// rs1 shifts
assign shift1 = rs1 >> 1;

4
src/ieu/sha_instructions/sha512sig1.sv
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@ -30,9 +30,7 @@ module sha512sig1(
output logic [63:0] result
);
logic [63:0] ror19;
logic [63:0] ror61;
logic [63:0] sh6;
logic [63:0] ror19, ror61, sh6;
assign ror19 = {rs1[18:0], rs1[63:19]};
assign ror61 = {rs1[60:0], rs1[63:61]};

11
src/ieu/sha_instructions/sha512sig1h.sv
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@ -31,18 +31,15 @@ module sha512sig1h(
output logic [31:0] DataOut
);
// rs1 shifts
logic [31:0] shift3;
logic [31:0] shift6;
logic [31:0] shift19;
// rs2 shifts
logic [31:0] shift29;
logic [31:0] shift13;
logic [31:0] shift3, shift6, shift19; // rs1 shifts
logic [31:0] shift29, shift13; // rs2 shifts
// shift rs1
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift19 = rs1 >> 19;
// shift rs2
assign shift29 = rs2 >> 29;
assign shift13 = rs2 << 13;

15
src/ieu/sha_instructions/sha512sig1l.sv
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@ -31,19 +31,12 @@ module sha512sig1l(
output logic [31:0] DataOut
);
// rs1 shift logic
logic [31:0] shift3;
logic [31:0] shift6;
logic [31:0] shift19;
// rs2 shift logics
logic [31:0] shift29;
logic [31:0] shift26;
logic [31:0] shift13;
logic [31:0] shift3, shift6, shift19; // rs1 shifts
logic [31:0] shift29, shift26, shift13;
// Shift rs1
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift19 = rs1 >> 19;
// Shift rs2

4
src/ieu/sha_instructions/sha512sum0.sv
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@ -30,9 +30,7 @@ module sha512sum0(
output logic [63:0] result
);
logic [63:0] ror28;
logic [63:0] ror34;
logic [63:0] ror39;
logic [63:0] ror28, ror34, ror39;
assign ror28 = {rs1[27:0], rs1[63:28]};
assign ror34 = {rs1[33:0], rs1[63:34]};

11
src/ieu/sha_instructions/sha512sum0r.sv
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@ -31,15 +31,8 @@ module sha512sum0r(
output logic [31:0] DataOut
);
// RS1 shifts
logic [31:0] shift25;
logic [31:0] shift30;
logic [31:0] shift28;
// RS2 shifts
logic [31:0] shift7;
logic [31:0] shift2;
logic [31:0] shift4;
logic [31:0] shift25, shift30, shift28; // rs1 shifts
logic [31:0] shift7, shift2, shift4; // rs2 shifts
// Shift rs1
assign shift25 = rs1 << 25;

6
src/ieu/sha_instructions/sha512sum1.sv
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@ -30,10 +30,8 @@ module sha512sum1(
output logic [63:0] result
);
logic [63:0] ror14;
logic [63:0] ror18;
logic [63:0] ror41;
logic [63:0] ror14, ror18, ror41;
assign ror14 = {rs1[13:0], rs1[63:14]};
assign ror18 = {rs1[17:0], rs1[63:18]};
assign ror41 = {rs1[40:0], rs1[63:41]};

13
src/ieu/sha_instructions/sha512sum1r.sv
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@ -31,15 +31,8 @@ module sha512sum1r(
output logic [31:0] DataOut
);
// Declare logic for rs1 shifts
logic [31:0] shift1by23;
logic [31:0] shift1by14;
logic [31:0] shift1by18;
// Declare logic for rs2 shifts
logic [31:0] shift2by9;
logic [31:0] shift2by18;
logic [31:0] shift2by14;
logic [31:0] shift1by23, shift1by14, shift1by18; // rs1 shifts
logic [31:0] shift2by9, shift2by18, shift2by14; // rs2 shifts
// Shift RS1
assign shift1by23 = rs1 << 23;
@ -47,7 +40,7 @@ module sha512sum1r(
assign shift1by18 = rs1 >> 18;
// Shift RS2
assign shift2by9 = rs2 >> 9;
assign shift2by9 = rs2 >> 9;
assign shift2by18 = rs2 << 18;
assign shift2by14 = rs2 << 14;