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minor changes + date change on copyright

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James E. Stine 2024-02-20 19:13:11 -06:00
parent 488583aed9
commit 93d9bb4bc4
11 changed files with 40 additions and 68 deletions
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6
src/ieu/aes_common/aes_inv_mixcolumns.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V AES Mix Columns
// Purpose: AES Inverted Mix Column Function for use with AES
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//

6
src/ieu/aes_common/aes_inv_sbox.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V Rinjdael Inverted S-BOX
// Purpose: Rinjdael Inverted S-BOX in form of a LUT
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//

14
src/ieu/aes_common/aes_inv_sbox_128.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V 128-bit Inverse Substitution box
// Purpose: 128-bit Inverse Substitution box comprised of 4x32-bit inverse s-boxes
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
@ -30,13 +28,13 @@
module aes_inv_sbox_128(input logic [127:0] in,
output logic [127:0] out);
//Declare the SBOX for (least significant) word 0 of the input
// Declare the SBOX for (least significant) word 0 of the input
aes_inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0]));
//Declare the SBOX for word 1 of the input
// Declare the SBOX for word 1 of the input
aes_inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32]));
//Declare the SBOX for word 2 of the input
// Declare the SBOX for word 2 of the input
aes_inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64]));
//Declare the SBOX for word 3 of the input
// Declare the SBOX for word 3 of the input
aes_inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96]));
endmodule

14
src/ieu/aes_common/aes_inv_sbox_word.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V Rinjdael Inverted S-BOX
// Purpose: 4 sets of Rinjdael Inverse S-BOX for whole word look up
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
@ -30,13 +28,13 @@
module aes_inv_sbox_word(input logic [31:0] in,
output logic [31:0] out);
//Declare the SBOX for (least significant) byte 0 of the input
// Declare the SBOX for (least significant) byte 0 of the input
aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
//Declare the SBOX for byte 1 of the input
// Declare the SBOX for byte 1 of the input
aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
//Declare the SBOX for byte 2 of the input
// Declare the SBOX for byte 2 of the input
aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16]));
//Declare the SBOX for byte 3 of the input
// Declare the SBOX for byte 3 of the input
aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
endmodule

17
src/ieu/aes_common/aes_inv_shiftrow.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V AES Shiftrow
// Purpose: AES Shiftrow
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
@ -30,27 +28,26 @@
module aes_inv_shiftrow(input logic [127:0] dataIn,
output logic [127:0] dataOut);
// Seperate the first (Least Significant) word into bytes
// Separate the first (Least Significant) word into bytes
logic [7:0] w0_b0 = dataIn[7:0];
logic [7:0] w0_b1 = dataIn[15:8];
logic [7:0] w0_b2 = dataIn[23:16];
logic [7:0] w0_b3 = dataIn[31:24];
// Seperate the second word into bytes
// Separate the second word into bytes
logic [7:0] w1_b0 = dataIn[39:32];
logic [7:0] w1_b1 = dataIn[47:40];
logic [7:0] w1_b2 = dataIn[55:48];
logic [7:0] w1_b3 = dataIn[63:56];
// Seperate the third word into bytes
// Separate the third word into bytes
logic [7:0] w2_b0 = dataIn[71:64];
logic [7:0] w2_b1 = dataIn[79:72];
logic [7:0] w2_b2 = dataIn[87:80];
logic [7:0] w2_b3 = dataIn[95:88];
// Seperate the fourth (Most significant) word into bytes
// Separate the fourth (Most significant) word into bytes
logic [7:0] w3_b0 = dataIn[103:96];
logic [7:0] w3_b1 = dataIn[111:104];
logic [7:0] w3_b2 = dataIn[119:112];
logic [7:0] w3_b3 = dataIn[127:120];
logic [7:0] w3_b3 = dataIn[127:120];
// The output words are composed of sets of the input bytes.
logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};

21
src/ieu/aes_common/aes_mixcolumns.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V "Mix Columns"
// Purpose: AES "Mix Columns" Operation
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
@ -76,17 +74,13 @@ module mixword (word, mixed_word);
// Declare Internal Signals
logic [7:0] b0, b1, b2, b3;
logic [7:0] mb0, mb1, mb2, mb3;
logic [7:0] mb0, mb1, mb2, mb3;
logic [7:0] gm2_0_out;
logic [7:0] gm3_0_out;
logic [7:0] gm3_0_out;
logic [7:0] gm2_1_out;
logic [7:0] gm3_1_out;
logic [7:0] gm3_1_out;
logic [7:0] gm2_2_out;
logic [7:0] gm3_2_out;
logic [7:0] gm3_2_out;
logic [7:0] gm2_3_out;
logic [7:0] gm3_3_out;
@ -99,15 +93,12 @@ module mixword (word, mixed_word);
// mb0 Galois components
gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out));
gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out));
// mb1 Galois components
gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out));
gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out));
// mb2 Galois components
gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out));
gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out));
// mb3 Galois components
gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out));
gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out));

6
src/ieu/aes_common/aes_sbox.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V Rinjdael forward S-BOX in the form of a LUT
// Purpose: Rinjdael forward S-BOX in the form of a LUT
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//

6
src/ieu/aes_common/aes_sbox_word.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously.
// Purpose: 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously.
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//

6
src/ieu/aes_common/aes_shiftrow.sv
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@ -4,14 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V aes_shiftrow for taking in first data line
// Purpose: aes_shiftrow for taking in first data line
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//

8
src/ieu/aes_common/galois_func.sv
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@ -1,17 +1,15 @@
///////////////////////////////////////////
// Galois_func.sv
// galois_func.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V Galois field operations for mix columns operation
// Purpose: Galois field operations for mix columns operation
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//

4
src/ieu/aes_common/rotateleft.sv
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@ -4,12 +4,12 @@
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V 32-bit left rotate
// Purpose: 32-bit left rotate for AES
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//