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Update K extension in SHA to remove redundant logic and optimize hierarchy to reduce structure/area

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This commit is contained in:
James Stine 2024-03-12 11:10:45 -05:00
parent ef2c003029
commit 55863bda1b
15 changed files with 123 additions and 493 deletions
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20
src/ieu/bmu/bmuctrl.sv
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@ -259,21 +259,21 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
if (P.XLEN==32)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0101110_000: BMUControlsD = `BMUCTRLW'b000_1000_0100_1_0_0_1_0_0_0_0_0; // sha512sig0h
17'b0110011_0101010_000: BMUControlsD = `BMUCTRLW'b000_1000_0101_1_0_0_1_0_0_0_0_0; // sha512sig0l
17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1000_0110_1_0_0_1_0_0_0_0_0; // sha512sig1h
17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1000_0111_1_0_0_1_0_0_0_0_0; // sha512sig1l
17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_1_0_0_0_0_0; // sha512sum0r
17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_1_0_0_0_0_0; // sha512sum1r
17'b0110011_0101110_000: BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_1_0_0_0_0_0; // sha512sig0h
17'b0110011_0101010_000: BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_1_0_0_0_0_0; // sha512sig0l
17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sig1h
17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sig1l
17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_1_0_0_0_0_0; // sha512sum0r
17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1101_1_0_0_1_0_0_0_0_0; // sha512sum1r
endcase
else if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0010011_0001000_001:
if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1000_0100_1_0_0_1_0_0_0_0_0; // sha512sig0
else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1000_0101_1_0_0_1_0_0_0_0_0; // sha512sig1
else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1000_0110_1_0_0_1_0_0_0_0_0; // sha512sum0
else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1000_0111_1_0_0_1_0_0_0_0_0; // sha512sum1
if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_1_0_0_0_0_0; // sha512sig0
else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_1_0_0_0_0_0; // sha512sig1
else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sum0
else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sum1
endcase
end
end

19
src/ieu/kmu/zknh32.sv
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@ -3,6 +3,7 @@
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 13 February 2024
// Modified: 12 March 2024
//
// Purpose: RISC-V ZKNH 32-Bit top level unit: RV32 NIST Hash
//
@ -26,14 +27,18 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module zknh32 (
input logic [31:0] A, B,
input logic [3:0] ZKNHSelect,
output logic [31:0] ZKNHResult
input logic [31:0] A, B,
input logic [3:0] ZKNHSelect,
output logic [31:0] ZKNHResult
);
logic [31:0] sha256sig0res, sha256sig1res, sha256sum0res, sha256sum1res;
logic [31:0] sha512sig0hres, sha512sig0lres, sha512sig1hres, sha512sig1lres, sha512sum0rres, sha512sum1rres;
logic [31:0] sha256res, sha512res;
sha256 sha256(A, ZKNHSelect[1:0], sha256res); // 256-bit SHA support: sha256{sig0/sig1/sum0/sum1}
sha512_32 sha512(A, B, ZKNHSelect[2:0], sha512res); // 512-bit SHA support: sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r}
mux2 #(32) resultmux(sha256res, sha512res, ZKNHSelect[3], ZKNHResult); // SHA256 vs. SHA512 result mux
/*
sha256sig0 #(32) sha256sig0(A, sha256sig0res);
sha256sig1 #(32) sha256sig1(A, sha256sig1res);
sha256sum0 #(32) sha256sum0(A, sha256sum0res);
@ -59,5 +64,5 @@ module zknh32 (
4'b1000: ZKNHResult = sha512sum0rres;
4'b1001: ZKNHResult = sha512sum1rres;
default: ZKNHResult = 0;
endcase
endcase */
endmodule

4
src/ieu/kmu/zknh64.sv
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@ -32,10 +32,10 @@ module zknh64 (
);
logic [31:0] sha256_32;
logic [63:0] sha256res, sha512res;
logic [63:0] sha256res, sha512res;
sha256 sha256(A[31:0], ZKNHSelect[1:0], sha256_32); // 256-bit SHA support: sha256{sig0/sig1/sum0/sum1}
assign sha256res = {{32{sha256_32[31]}}, sha256_32}; // sign-extend 256-bit result from 32 to 64 bits
sha512_64 sha512(A, ZKNHSelect[1:0], sha512res); // 512-bit SHA support: sha512{sig0/sig1/sum0/sum1}
mux2 #(64) resultmux(sha256res, sha512res, ZKNHSelect[2], ZKNHResult); // SHA256 vs. SHA512 result mux
mux2 #(64) resultmux(sha256res, sha512res, ZKNHSelect[3], ZKNHResult); // SHA256 vs. SHA512 result mux
endmodule

45
src/ieu/sha/sha256sig0.sv
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@ -1,45 +0,0 @@
///////////////////////////////////////////
// sha256sig0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sig0 instruction: SHA2-256 Sigma0
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sig0 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result
);
logic [31:0] ror7, ror18, sh3, exts;
assign ror7 = {rs1[6:0], rs1[31:7]};
assign ror18 = {rs1[17:0], rs1[31:18]};
assign sh3 = {3'b0, rs1[31:3]};
// Assign output to xor of 3 rotates
assign exts = ror7 ^ ror18 ^ sh3;
// Sign-extend for RV64
if (WIDTH==32) assign result = exts;
else assign result = {{32{exts[31]}}, exts};
endmodule

45
src/ieu/sha/sha256sig1.sv
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@ -1,45 +0,0 @@
///////////////////////////////////////////
// sha256sig1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sig1 instruction: SHA2-256 Sigma1
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sig1 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result
);
logic [31:0] ror17, ror19, sh10, exts;
assign ror17 = {rs1[16:0], rs1[31:17]};
assign ror19 = {rs1[18:0], rs1[31:19]};
assign sh10 = {10'b0, rs1[31:10]};
// Assign output to xor of 3 rotates
assign exts = ror17 ^ ror19 ^ sh10;
// Sign-extend for RV64
if (WIDTH==32) assign result = exts;
else assign result = {{32{exts[31]}}, exts};
endmodule

45
src/ieu/sha/sha256sum0.sv
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@ -1,45 +0,0 @@
///////////////////////////////////////////
// sha256sum0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sum0 instruction: : SHA2-256 Sum0
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sum0 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result
);
logic [31:0] ror2, ror13, ror22, exts;
assign ror2 = {rs1[1:0], rs1[31:2]};
assign ror13 = {rs1[12:0], rs1[31:13]};
assign ror22 = {rs1[21:0], rs1[31:22]};
// Assign output to xor of 3 rotates
assign exts = ror2 ^ ror13 ^ ror22;
// Sign-extend for RV64
if (WIDTH==32) assign result = exts;
else assign result = {{32{exts[31]}}, exts};
endmodule

45
src/ieu/sha/sha256sum1.sv
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@ -1,45 +0,0 @@
///////////////////////////////////////////
// sha256sum1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sum1 instruction: : SHA2-256 Sum1
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sum1 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result
);
logic [31:0] ror6, ror11, ror25, exts;
assign ror6 = {rs1[5:0], rs1[31:6]};
assign ror11 = {rs1[10:0], rs1[31:11]};
assign ror25 = {rs1[24:0], rs1[31:25]};
// Assign output to xor of 3 rotates
assign exts = ror6 ^ ror11 ^ ror25;
// Sign-extend for RV64
if (WIDTH==32) assign result = exts;
else assign result = {{32{exts[31]}}, exts};
endmodule

97
src/ieu/sha/sha512_32.sv Normal file
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@ -0,0 +1,97 @@
///////////////////////////////////////////
// sha512_32.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 13 February 2024
//
// Purpose: RISC-V (RV32) ZKNH 512-bit SHA: select shifted inputs and XOR6
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512_32 (
input logic [31:0] A, B,
input logic [2:0] ZKNHSelect,
output logic [31:0] result
);
logic [31:0] x[6][6];
logic [31:0] y[6];
// sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r} select shifted operands for 32-bit xor6
// sha512sig0h
assign x[0][0] = A >> 1;
assign x[0][1] = A >> 7;
assign x[0][2] = A >> 8;
assign x[0][3] = B << 31;
assign x[0][4] = B << 24;
assign x[0][5] = 0;
// sha512sig0l
assign x[1][0] = A >> 1;
assign x[1][1] = A >> 7;
assign x[1][2] = A >> 8;
assign x[1][3] = B << 31;
assign x[1][4] = B << 25;
assign x[1][5] = B << 24;
// sha512sig1h
assign x[2][0] = A << 3;
assign x[2][1] = A >> 6;
assign x[2][2] = A >> 19;
assign x[2][3] = B >> 29;
assign x[2][4] = B << 13;
assign x[2][5] = 0;
// sha512sig1l
assign x[3][0] = A << 3;
assign x[3][1] = A >> 6;
assign x[3][2] = A >> 19;
assign x[3][3] = B >> 29;
assign x[3][4] = B << 26;
assign x[3][5] = B << 13;
// sha512sum0r
assign x[4][0] = A << 25;
assign x[4][1] = A << 30;
assign x[4][2] = A >> 28;
assign x[4][3] = B >> 7;
assign x[4][4] = B >> 2;
assign x[4][5] = B << 4;
// sha512sum1r
assign x[5][0] = A << 23;
assign x[5][1] = A >> 14;
assign x[5][2] = A >> 18;
assign x[5][3] = B >> 9;
assign x[5][4] = B << 18;
assign x[5][5] = B << 14;
// 32-bit muxes to select inputs to xor6 for sha512
assign y[0] = x[ZKNHSelect[2:0]][0];
assign y[1] = x[ZKNHSelect[2:0]][1];
assign y[2] = x[ZKNHSelect[2:0]][2];
assign y[3] = x[ZKNHSelect[2:0]][3];
assign y[4] = x[ZKNHSelect[2:0]][4];
assign y[5] = x[ZKNHSelect[2:0]][5];
// sha512 32-bit xor6
assign result = y[0] ^ y[1] ^ y[2] ^ y[3] ^ y[4] ^ y[5];
endmodule

4
src/ieu/sha/sha512_64.sv
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@ -4,7 +4,7 @@
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 13 February 2024
//
// Purpose: RISC-V ZKNH 512-bit SHA: select shifted inputs and XOR3
// Purpose: RISC-V (RV64) ZKNH 512-bit SHA: select shifted inputs and XOR3
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
@ -56,7 +56,7 @@ module sha512_64 (
assign x[3][1] = {A[17:0], A[63:18]};
assign x[3][2] = {A[40:0], A[63:41]};
// 64-bit muxes to select inputs to xor3 for sha256
// 64-bit muxes to select inputs to xor3 for sha512
assign y[0] = x[ZKNHSelect[1:0]][0];
assign y[1] = x[ZKNHSelect[1:0]][1];
assign y[2] = x[ZKNHSelect[1:0]][2];

48
src/ieu/sha/sha512sig0h.sv
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@ -1,48 +0,0 @@
///////////////////////////////////////////
// sha512sig0h.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig0h instruction: RV32 SHA2-512 Sigma0 high instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0h(
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
);
logic [31:0] shift1, shift7, shift8; // rs1 shifts
logic [31:0] shift31, shift24; // rs2 shifts
// Shift rs1
assign shift1 = rs1 >> 1;
assign shift7 = rs1 >> 7;
assign shift8 = rs1 >> 8;
// Shift rs2
assign shift31 = rs2 << 31;
assign shift24 = rs2 << 24;
// XOR to get result
assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24;
endmodule

48
src/ieu/sha/sha512sig0l.sv
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@ -1,48 +0,0 @@
///////////////////////////////////////////
// sha512sig0l.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig0l instruction: : RV32 SHA2-512 Sigma0 low instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0l(
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
);
logic [31:0] shift1, shift7, shift8; // rs1 shifts
logic [31:0] shift31, shift25, shift24; // rs2 shifts
// rs1 shifts
assign shift1 = rs1 >> 1;
assign shift7 = rs1 >> 7;
assign shift8 = rs1 >> 8;
// rs2 shifts
assign shift31 = rs2 << 31;
assign shift25 = rs2 << 25;
assign shift24 = rs2 << 24;
assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24;
endmodule

50
src/ieu/sha/sha512sig1h.sv
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@ -1,50 +0,0 @@
///////////////////////////////////////////
// sha512sig1h.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig1h instruction: : RV32 SHA2-512 Sigma1 high instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1h(
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
);
logic [31:0] shift3, shift6, shift19; // rs1 shifts
logic [31:0] shift29, shift13; // rs2 shifts
// shift rs1
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift19 = rs1 >> 19;
// shift rs2
assign shift29 = rs2 >> 29;
assign shift13 = rs2 << 13;
// XOR Shifted registers for output
assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13;
endmodule

48
src/ieu/sha/sha512sig1l.sv
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@ -1,48 +0,0 @@
///////////////////////////////////////////
// sha512sig1l.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig1l instruction: : RV32 SHA2-512 Sigma1 low instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1l(
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
);
logic [31:0] shift3, shift6, shift19; // rs1 shifts
logic [31:0] shift29, shift26, shift13; // rs2 shifts
// Shift rs1
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift19 = rs1 >> 19;
// Shift rs2
assign shift29 = rs2 >> 29;
assign shift26 = rs2 << 26;
assign shift13 = rs2 << 13;
assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13;
endmodule

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@ -1,49 +0,0 @@
///////////////////////////////////////////
// sha512sum0r.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum0r instruction: RV32 SHA2-512 Sum0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum0r(
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
);
logic [31:0] shift25, shift30, shift28; // rs1 shifts
logic [31:0] shift7, shift2, shift4; // rs2 shifts
// Shift rs1
assign shift25 = rs1 << 25;
assign shift30 = rs1 << 30;
assign shift28 = rs1 >> 28;
// Shift rs2
assign shift7 = rs2 >> 7;
assign shift2 = rs2 >> 2;
assign shift4 = rs2 << 4;
// Set output to XOR of shifted values
assign DataOut = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4;
endmodule

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///////////////////////////////////////////
// sha512sum1r.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum1r instruction: RV32 SHA2-512 Sum01instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum1r(
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut
);
logic [31:0] shift1by23, shift1by14, shift1by18; // rs1 shifts
logic [31:0] shift2by9, shift2by18, shift2by14; // rs2 shifts
// Shift RS1
assign shift1by23 = rs1 << 23;
assign shift1by14 = rs1 >> 14;
assign shift1by18 = rs1 >> 18;
// Shift RS2
assign shift2by9 = rs2 >> 9;
assign shift2by18 = rs2 << 18;
assign shift2by14 = rs2 << 14;
// Assign output to xor of shifts
assign DataOut = shift1by23 ^ shift1by14 ^ shift1by18 ^ shift2by9 ^ shift2by18 ^ shift2by14;
endmodule