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Don't want to clear the lru bits on invalidation (clearvalid).

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This commit is contained in:
Rose Thompson 2024-03-04 17:52:41 -06:00
parent a22de45631
commit 0222e8f42a
1 changed files with 1 additions and 3 deletions
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4
src/cache/cacheLRU.sv vendored
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@ -144,9 +144,7 @@ module cacheLRU
always_ff @(posedge clk) begin
if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; // exclusion-tag: initialize
if(CacheEn) begin
if(ClearValid & ~FlushStage)
LRUMemory[PAdr] <= '0;
else if(LRUWriteEn)
if(LRUWriteEn)
LRUMemory[PAdr] <= NextLRU;
if(LRUWriteEn & (PAdr == CacheSetTag))
CurrLRU <= #1 NextLRU;