mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 17:55:19 +00:00
Merging PR738
This commit is contained in:
David Harris
commit
571b67f565
@ -12,7 +12,6 @@
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##################################
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import sys,os,shutil
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import multiprocessing
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#import os
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from collections import namedtuple
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from multiprocessing import Pool, TimeoutError
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@ -24,7 +23,6 @@ from multiprocessing import Pool, TimeoutError
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# The element consists of the configuration name, a list of test suites to run,
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# optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
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INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
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tests = [
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["rv32e", ["arch32e"]],
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["rv32i", ["arch32i"]],
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@ -34,10 +32,22 @@ tests = [
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"arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
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"arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zcb",
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"arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zfad" # fcvtmod.w.d not working because of Sail flag bug. Jordan has PR in to fix Sail
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["rv64i", ["arch64i"]],
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["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"]
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["rv64i", ["arch64i"]]
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]
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# Separate test for full buildroot run
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tests_buildrootshort = [
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["buildroot", ["buildroot"], [f"+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output
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"OpenSBI v", "buildroot_uart.out"]
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]
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tests_buildrootboot = [
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["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], # boot entire buildroot Linux to login prompt
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"WallyHostname login: ", "buildroot_uart.out"]
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]
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# Separate out floating-point tests for RV64 to speed up coverage
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tests64gc_nofp = [
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["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
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@ -176,7 +186,7 @@ bpredtests = [
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# Data Types & Functions
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##################################
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TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
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TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile'])
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# name: the name of this test configuration (used in printing human-readable
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# output and picking logfile names)
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# cmd: the command to run to test (should include the logfile as '{}', and
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@ -184,6 +194,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
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# grepstr: the string to grep through the log file for. The test succeeds iff
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# grep finds that string in the logfile (is used by grep, so it may
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# be any pattern grep accepts, see `man 1 grep` for more info).
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# grepfile: a string containing the location of the file to be searched for output
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class bcolors:
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HEADER = '\033[95m'
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@ -197,6 +208,7 @@ class bcolors:
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UNDERLINE = '\033[4m'
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def addTests(tests, sim):
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sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
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for test in tests:
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config = test[0];
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suites = test[1];
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@ -210,36 +222,38 @@ def addTests(tests, sim):
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gs = "All tests ran without failures"
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cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
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for t in suites:
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sim_log = sim_logdir + config + "_" + t + ".log"
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if (len(test) >= 5):
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grepfile = sim_logdir + test[4]
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else:
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grepfile = sim_log
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tc = TestCase(
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name=t,
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variant=config,
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cmd=cmdPrefix + " " + t + args,
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grepstr=gs)
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cmd=cmdPrefix + " " + t + args + " > " + sim_log,
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grepstr=gs,
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grepfile = grepfile)
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configs.append(tc)
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def search_log_for_text(text, logfile):
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def search_log_for_text(text, grepfile):
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"""Search through the given log file for text, returning True if it is found or False if it is not"""
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grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
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grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile)
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# print(" search_log_for_text invoking %s" % grepcmd)
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return os.system(grepcmd) == 0
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def run_test_case(config):
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"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
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logname = WALLY + "/sim/questa/logs/"+config.variant+"_"+config.name+".log" ### *** fix hardwiring to questa log
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#cmd = config.cmd + " > " + logname
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if ("lint-wally" in config.cmd):
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cmd = config.cmd + " | tee " + logname
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else:
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cmd = config.cmd + " > " + logname
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grepfile = config.grepfile
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cmd = config.cmd
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os.chdir(regressionDir)
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# print(" run_test_case invoking %s" % cmd)
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# print(" run_test_case invoking %s" % cmd)
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os.system(cmd)
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if search_log_for_text(config.grepstr, logname):
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if search_log_for_text(config.grepstr, grepfile):
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print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
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return 0
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else:
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print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
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print(" Check %s" % logname)
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print(" Check %s" % grepfile)
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return 1
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##################################
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@ -258,13 +272,14 @@ coverage = '--coverage' in sys.argv
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fp = '--fp' in sys.argv
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nightly = '--nightly' in sys.argv
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testfloat = '--testfloat' in sys.argv
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buildroot = '--buildroot' in sys.argv
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if (nightly):
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nightMode = "--nightly";
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# sims = ["questa", "verilator", "vcs"]
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sims = ["verilator"] # *** uncomment to exercise all simulators
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else:
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nightMode = "";
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nightMode = ""
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sims = [defaultsim]
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if (coverage): # only run RV64GC tests in coverage mode
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@ -278,9 +293,9 @@ configs = [
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TestCase(
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name="lints",
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variant="all",
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cmd="lint-wally " + nightMode,
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grepstr="lints run with no errors or warnings"
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)
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cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/questa/logs/all_lints.log",
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grepstr="lints run with no errors or warnings",
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grepfile = WALLY + "/sim/questa/logs/all_lints.log")
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]
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if (coverage): # only run RV64GC tests on Questa in coverage mode
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@ -292,9 +307,13 @@ else:
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addTests(tests, sim)
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addTests(tests64gc_nofp, sim)
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addTests(tests64gc_fp, sim)
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# run derivative configurations in nightly regression
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if (nightly):
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addTests(derivconfigtests, defaultsim)
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if (nightly):
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addTests(derivconfigtests, defaultsim)
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addTests(tests_buildrootboot, defaultsim)
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else:
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addTests(tests_buildrootshort, defaultsim)
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# testfloat tests
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if (testfloat):
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@ -306,11 +325,13 @@ if (testfloat):
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if ("f_" in config):
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tests.remove("cvtfp")
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for test in tests:
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sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log" # TODO: Change hardcoded questa log directory to simulator
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tc = TestCase(
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name=test,
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variant=config,
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cmd="wsim --tb testbench_fp " + config + " " + test,
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grepstr="All Tests completed with 0 errors")
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cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log,
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grepstr="All Tests completed with 0 errors",
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grepfile = sim_log)
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configs.append(tc)
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@ -349,11 +370,13 @@ if (testfloat):
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if ("f_" in config):
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tests.remove("cvtfp")
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for test in tests:
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sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log"
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tc = TestCase(
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name=test,
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variant=config,
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cmd="wsim --tb testbench_fp --sim questa " + config + " " + test,
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grepstr="All Tests completed with 0 errors")
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cmd="wsim --tb testbench_fp --sim questa " + config + " " + test + " > " + sim_log,
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grepstr="All Tests completed with 0 errors",
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grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log")
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configs.append(tc)
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@ -371,26 +394,17 @@ def main():
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os.chdir(regressionDir)
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os.system('./make-tests.sh | tee ./logs/make-tests.log')
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if '--all' in sys.argv:
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TIMEOUT_DUR = 30*7200 # seconds
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#configs.append(getBuildrootTC(boot=True))
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elif '--buildroot' in sys.argv:
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TIMEOUT_DUR = 30*7200 # seconds
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#configs=[getBuildrootTC(boot=True)]
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if '--buildroot' in sys.argv:
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TIMEOUT_DUR = 60*7200 # 5 days to run
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elif '--coverage' in sys.argv:
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TIMEOUT_DUR = 20*60 # seconds
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# Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
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# Also it is slow to run.
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# configs.append(getBuildrootTC(boot=False))
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TIMEOUT_DUR = 20*60 # seconds
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os.system('rm -f questa/cov/*.ucdb')
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elif '--nightly' in sys.argv:
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TIMEOUT_DUR = 60*1440 # 1 day
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#configs.append(getBuildrootTC(boot=False))
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elif '--testfloat' in sys.argv:
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TIMEOUT_DUR = 5*60 # seconds
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else:
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TIMEOUT_DUR = 10*60 # seconds
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#configs.append(getBuildrootTC(boot=False))
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# Scale the number of concurrent processes to the number of test cases, but
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# max out at a limited number of concurrent processes to not overwhelm the system
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@ -471,88 +471,88 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
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add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR
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add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS
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add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY
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add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
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add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
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add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
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add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
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add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
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add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
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add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
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add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt
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add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/Dout
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add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim
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add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn
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add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress
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||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending
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add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority
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add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold
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||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending
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||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests
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||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix
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||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs
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||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs
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||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority
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||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
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||||
add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
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||||
add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
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add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL
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||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWDATA
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWRITE
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/intrID
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
|
||||
add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HADDR
|
||||
add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HTRANS
|
||||
add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HREADY
|
||||
add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELRegions
|
||||
add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELNoneD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELPLICD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HRDATA
|
||||
add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/MExtInt
|
||||
add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/SExtInt
|
||||
add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/Dout
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intClaim
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intEn
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intInProgress
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPending
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPriority
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intThreshold
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/nextIntPending
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/requests
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqMatrix
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/priorities_with_irqs
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/max_priority_with_irqs
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqs_at_max_priority
|
||||
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/threshMask
|
||||
add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSEL
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PADDR
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWDATA
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSTRB
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWRITE
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PENABLE
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PRDATA
|
||||
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PREADY
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LSR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MCR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MSR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RBR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/TXHR
|
||||
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LCR
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/intrID
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/INTR
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxstate
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txstate
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitssent
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitsexpected
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsreceived
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsexpected
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdata
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxoverrunerr
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataready
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataavailintr
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RXBR
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/squashRXerrIP
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxshiftreg
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SOUTbit
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SINsync
|
||||
add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txsr
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SIN
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SOUT
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RTSb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DTRb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT1b
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT2b
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DSRb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DCDb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/CTSb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/TXRDYb
|
||||
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RXRDYb
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIN
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOOUT
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOEN
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSEL
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PADDR
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWRITE
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PRDATA
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PREADY
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWDATA
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSTRB
|
||||
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PENABLE
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rf
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
|
||||
|
||||
@ -31,7 +31,6 @@ import "DPI-C" function string getenvval(input string env_name);
|
||||
`else
|
||||
import "DPI-C" function string getenv(input string env_name);
|
||||
`endif
|
||||
import "DPI-C" function int system(input string env_name);
|
||||
|
||||
module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
|
||||
(input logic clk,
|
||||
|
||||
@ -39,7 +39,6 @@ import "DPI-C" function string getenvval(input string env_name);
|
||||
`else
|
||||
import "DPI-C" function string getenv(input string env_name);
|
||||
`endif
|
||||
import "DPI-C" function int system(input string env_name);
|
||||
|
||||
module testbench;
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
@ -254,8 +253,9 @@ module testbench;
|
||||
logic ResetCntRst;
|
||||
logic CopyRAM;
|
||||
|
||||
string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
|
||||
string signame, memfilename, bootmemfilename, uartoutfilename, pathname;
|
||||
integer begin_signature_addr, end_signature_addr, signature_size;
|
||||
integer uartoutfile;
|
||||
|
||||
assign ResetThreshold = 3'd5;
|
||||
|
||||
@ -328,8 +328,6 @@ module testbench;
|
||||
else
|
||||
assign EcallFaultM = 0;
|
||||
|
||||
// this is an unused integer for the return value of `system`
|
||||
int unused_int;
|
||||
always @(posedge clk) begin
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Verify the test ran correctly by checking the memory against a known signature.
|
||||
@ -355,8 +353,7 @@ module testbench;
|
||||
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
||||
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
||||
uartoutfilename = {"logs/", TEST, "_uart.out"};
|
||||
rmCmd = {"rm -f ", uartoutfilename};
|
||||
unused_int = system(rmCmd); // Delete existing UARToutfile
|
||||
uartoutfile = $fopen(uartoutfilename, "wb");
|
||||
end
|
||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
if (riscofTest) begin
|
||||
@ -383,6 +380,8 @@ module testbench;
|
||||
always @(posedge Validate) // added
|
||||
`endif
|
||||
if(Validate) begin
|
||||
if (TEST == "buildroot")
|
||||
$fclose(uartoutfile);
|
||||
if (TEST == "embench") begin
|
||||
// Writes contents of begin_signature to .sim.output file
|
||||
// this contains instret and cycles for start and end of test run, used by embench
|
||||
@ -602,9 +601,7 @@ module testbench;
|
||||
always @(posedge clk) begin
|
||||
if (TEST == "buildroot") begin
|
||||
if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
|
||||
memFile = $fopen(uartoutfilename, "ab");
|
||||
$fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
|
||||
$fclose(memFile);
|
||||
$fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user