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Simplified ZKNH64

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This commit is contained in:
David Harris 2024-03-11 09:41:36 -07:00
parent dbfe44a54b
commit 7132d306b4
7 changed files with 113 additions and 163 deletions
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8
src/ieu/bmu/bmuctrl.sv
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@ -270,10 +270,10 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
else if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0010011_0001000_001:
if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sig0
else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sig1
else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_1_0_0_0_0_0; // sha512sum0
else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1000_1101_1_0_0_1_0_0_0_0_0; // sha512sum1
if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1000_0100_1_0_0_1_0_0_0_0_0; // sha512sig0
else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1000_0101_1_0_0_1_0_0_0_0_0; // sha512sig1
else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1000_0110_1_0_0_1_0_0_0_0_0; // sha512sum0
else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1000_0111_1_0_0_1_0_0_0_0_0; // sha512sum1
endcase
end
end

30
src/ieu/kmu/zknh64.sv
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@ -31,29 +31,11 @@ module zknh64 (
output logic [63:0] ZKNHResult
);
logic [63:0] sha256sig0res, sha256sig1res, sha256sum0res, sha256sum1res;
logic [63:0] sha512sig0res, sha512sig1res, sha512sum0res, sha512sum1res;
logic [31:0] sha256_32;
logic [63:0] sha256res, sha512res;
sha256sig0 #(64) sha256sig0(A, sha256sig0res);
sha256sig1 #(64) sha256sig1(A, sha256sig1res);
sha256sum0 #(64) sha256sum0(A, sha256sum0res);
sha256sum1 #(64) sha256sum1(A, sha256sum1res);
sha512sig0 sha512sig0(A, sha512sig0res);
sha512sig1 sha512sig1(A, sha512sig1res);
sha512sum0 sha512sum0(A, sha512sum0res);
sha512sum1 sha512sum1(A, sha512sum1res);
// Result Select Mux
always_comb
casez(ZKNHSelect)
4'b0000: ZKNHResult = sha256sig0res;
4'b0001: ZKNHResult = sha256sig1res;
4'b0010: ZKNHResult = sha256sum0res;
4'b0011: ZKNHResult = sha256sum1res;
4'b1010: ZKNHResult = sha512sig0res;
4'b1011: ZKNHResult = sha512sig1res;
4'b1100: ZKNHResult = sha512sum0res;
4'b1101: ZKNHResult = sha512sum1res;
default: ZKNHResult = 0;
endcase
sha256 sha256(A[31:0], ZKNHSelect[1:0], sha256_32); // 256-bit SHA support: sha256{sig0/sig1/sum0/sum1}
assign sha256res = {{32{sha256_32[31]}}, sha256_32}; // sign-extend 256-bit result from 32 to 64 bits
sha512_64 sha512(A, ZKNHSelect[1:0], sha512res); // 512-bit SHA support: sha512{sig0/sig1/sum0/sum1}
mux2 #(64) resultmux(sha256res, sha512res, ZKNHSelect[2], ZKNHResult); // SHA256 vs. SHA512 result mux
endmodule

66
src/ieu/sha/sha256.sv Normal file
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@ -0,0 +1,66 @@
///////////////////////////////////////////
// sha256.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 13 February 2024
//
// Purpose: RISC-V ZKNH 256-bit SHA: select shifted inputs and XOR3
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256 (
input logic [31:0] A,
input logic [1:0] ZKNHSelect,
output logic [31:0] result
);
logic [31:0] x[4][3];
logic [31:0] y[3];
// sha256{sig0/sig1/sum0/sum1} select shifted operands for 32-bit xor3 and then sign-extend
// sha256sig0
assign x[0][0] = {A[6:0], A[31:7]};
assign x[0][1] = {A[17:0], A[31:18]};
assign x[0][2] = {3'b0, A[31:3]};
// sha256sig1
assign x[1][0] = {A[16:0], A[31:17]};
assign x[1][1] = {A[18:0], A[31:19]};
assign x[1][2] = {10'b0, A[31:10]};
// sha256sum0
assign x[2][0] = {A[1:0], A[31:2]};
assign x[2][1] = {A[12:0], A[31:13]};
assign x[2][2] = {A[21:0], A[31:22]};
// sha256sum1
assign x[3][0] = {A[5:0], A[31:6]};
assign x[3][1] ={A[10:0], A[31:11]};
assign x[3][2] = {A[24:0], A[31:25]};
// 32-bit muxes to select inputs to xor3 for sha256
assign y[0] = x[ZKNHSelect[1:0]][0];
assign y[1] = x[ZKNHSelect[1:0]][1];
assign y[2] = x[ZKNHSelect[1:0]][2];
// sha256 32-bit xor3
assign result = y[0] ^ y[1] ^ y[2];
endmodule

49
src/ieu/sha/sha512sig0.sv → src/ieu/sha/sha512_64.sv
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@ -1,10 +1,10 @@
///////////////////////////////////////////
// sha512sig0.sv
// sha512_64.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
// Created: 13 February 2024
//
// Purpose: sha512sig0 instruction: RV64 SHA2-512 Sigma0 instruction
// Purpose: RISC-V ZKNH 512-bit SHA: select shifted inputs and XOR3
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
@ -25,17 +25,42 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0(
input logic [63:0] rs1,
module sha512_64 (
input logic [63:0] A,
input logic [1:0] ZKNHSelect,
output logic [63:0] result
);
logic [63:0] ror1, ror8, sh7;
logic [63:0] x[4][3];
logic [63:0] y[3];
assign ror1 = {rs1[0], rs1[63:1]};
assign ror8 = {rs1[7:0], rs1[63:8]};
assign sh7 = rs1 >> 7;
// Assign output to xor of 3 rotates
assign result = ror1 ^ ror8 ^ sh7;
// sha512{sig0/sig1/sum0/sum1} select shifted operands for 64-bit xor3
// sha512sig0
assign x[0][0] = {A[0], A[63:1]};
assign x[0][1] = {A[7:0], A[63:8]};
assign x[0][2] = A >> 7;
// sha512sig1
assign x[1][0] = {A[18:0], A[63:19]};
assign x[1][1] = {A[60:0], A[63:61]};
assign x[1][2] = A >> 6;
// sha512sum0
assign x[2][0] = {A[27:0], A[63:28]};
assign x[2][1] = {A[33:0], A[63:34]};
assign x[2][2] = {A[38:0], A[63:39]};
// sha512sum1
assign x[3][0] = {A[13:0], A[63:14]};
assign x[3][1] = {A[17:0], A[63:18]};
assign x[3][2] = {A[40:0], A[63:41]};
// 64-bit muxes to select inputs to xor3 for sha256
assign y[0] = x[ZKNHSelect[1:0]][0];
assign y[1] = x[ZKNHSelect[1:0]][1];
assign y[2] = x[ZKNHSelect[1:0]][2];
// sha512 64-bit xor3
assign result = y[0] ^ y[1] ^ y[2];
endmodule

41
src/ieu/sha/sha512sig1.sv
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@ -1,41 +0,0 @@
///////////////////////////////////////////
// sha512sig1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sig1 instruction: RV64 SHA2-512 Sigma1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1(
input logic [63:0] rs1,
output logic [63:0] result
);
logic [63:0] ror19, ror61, sh6;
assign ror19 = {rs1[18:0], rs1[63:19]};
assign ror61 = {rs1[60:0], rs1[63:61]};
assign sh6 = rs1 >> 6;
// Assign output to xor of 3 rotates
assign result = ror19 ^ ror61 ^ sh6;
endmodule

41
src/ieu/sha/sha512sum0.sv
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@ -1,41 +0,0 @@
///////////////////////////////////////////
// sha512sum0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum0 instruction: RV64 SHA2-512 Sum0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum0(
input logic [63:0] rs1,
output logic [63:0] result
);
logic [63:0] ror28, ror34, ror39;
assign ror28 = {rs1[27:0], rs1[63:28]};
assign ror34 = {rs1[33:0], rs1[63:34]};
assign ror39 = {rs1[38:0], rs1[63:39]};
// Assign output to xor of 3 rotates
assign result = ror28 ^ ror34 ^ ror39;
endmodule

41
src/ieu/sha/sha512sum1.sv
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@ -1,41 +0,0 @@
///////////////////////////////////////////
// sha512sum1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum1 instruction: RV64 SHA2-512 Sum1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum1(
input logic [63:0] rs1,
output logic [63:0] result
);
logic [63:0] ror14, ror18, ror41;
assign ror14 = {rs1[13:0], rs1[63:14]};
assign ror18 = {rs1[17:0], rs1[63:18]};
assign ror41 = {rs1[40:0], rs1[63:41]};
// Assign output to xor of 3 rotates
assign result = ror14 ^ ror18 ^ ror41;
endmodule