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https://github.com/openhwgroup/cvw
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Packetizer cleanup.
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@ -34,13 +34,6 @@ module packetizer import cvw::*; #(parameter cvw_t P,
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input logic m_axi_aclk, m_axi_aresetn,
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output logic RVVIStall,
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// axi 4 write address channel
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output logic [3:0] m_axi_awid,
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output logic [12:0] m_axi_awaddr,
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output logic [7:0] m_axi_awlen,
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output logic [2:0] m_axi_awsize,
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output logic [1:0] m_axi_awburst,
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output logic [3:0] m_axi_awcache,
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output logic m_axi_awvalid,
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input logic m_axi_awready,
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// axi 4 write data channel
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output logic [31:0] m_axi_wdata,
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@ -122,13 +115,6 @@ module packetizer import cvw::*; #(parameter cvw_t P,
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assign BytesInFrame = 12'd76;
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assign BurstDone = WordCount == (BytesInFrame[11:2] - 1'b1);
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assign m_axi_awid = '0;
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assign m_axi_awaddr = '0; // *** bug update to be based on the correct address during each beat.
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assign m_axi_awlen = BytesInFrame[11:2];
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assign m_axi_awsize = 3'b010; // 4 bytes
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assign m_axi_awburst = 2'b01; // increment
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assign m_axi_awcache = '0;
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assign m_axi_awvalid = (CurrState == STATE_RDY & valid) | CurrState == STATE_TRANS;
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genvar index;
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for (index = 0; index < TotalFrameLengthBytes/4; index++) begin
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assign TotalFrameWords[index] = TotalFrame[(index*32)+32-1 : (index*32)];
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@ -601,13 +601,6 @@ module testbench;
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// but I switched to using https://github.com/alexforencich/verilog-ethernet
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// so most arn't needed anymore. *** remove once I've confirmed this
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// works in synthesis.
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logic [3:0] m_axi_awid;
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logic [12:0] m_axi_awaddr;
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logic [7:0] m_axi_awlen;
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logic [2:0] m_axi_awsize;
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logic [1:0] m_axi_awburst;
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logic [3:0] m_axi_awcache;
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logic m_axi_awvalid;
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logic m_axi_awready;
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// axi 4 write data channel
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logic [31:0] m_axi_wdata;
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@ -644,7 +637,6 @@ module testbench;
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logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
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packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
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.m_axi_awid, .m_axi_awaddr, .m_axi_awlen, .m_axi_awsize, .m_axi_awburst, .m_axi_awcache, .m_axi_awvalid,
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.m_axi_awready, .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready, .m_axi_bid,
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.m_axi_bresp, .m_axi_bvalid, .m_axi_bready, .m_axi_arid, .m_axi_araddr, .m_axi_arlen, .m_axi_arsize,
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.m_axi_arburst, .m_axi_arcache, .m_axi_arvalid, .m_axi_arready, .m_axi_rid, .m_axi_rdata, .m_axi_rresp,
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