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https://github.com/openhwgroup/cvw
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Changed cachefsm state STATE_HIT to STATE_ACCESS.
This commit is contained in:
Rose Thompson
parent
85691f0e8b
commit
e72880fd89
42
src/cache/cachefsm.sv
vendored
42
src/cache/cachefsm.sv
vendored
@ -79,7 +79,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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logic CMOZeroNoEviction;
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logic StallConditions;
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typedef enum logic [3:0]{STATE_HIT, // hit states
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typedef enum logic [3:0]{STATE_ACCESS, // hit states
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// miss states
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STATE_FETCH,
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STATE_WRITEBACK,
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@ -101,7 +101,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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assign FlushFlag = FlushAdrFlag & FlushWayFlag;
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// outputs for the performance counters.
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assign CacheAccess = (|CacheRW) & ((CurrState == STATE_HIT & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
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assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
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assign CacheMiss = CacheAccess & ~CacheHit;
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// special case on reset. When the fsm first exists reset twayhe
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@ -110,22 +110,22 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
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always_ff @(posedge clk)
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if (reset | FlushStage) CurrState <= #1 STATE_HIT;
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if (reset | FlushStage) CurrState <= #1 STATE_ACCESS;
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else CurrState <= #1 NextState;
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always_comb begin
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NextState = STATE_HIT;
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NextState = STATE_ACCESS;
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case (CurrState) // exclusion-tag: icache state-case
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STATE_HIT: if(InvalidateCache) NextState = STATE_HIT; // exclusion-tag: dcache InvalidateCheck
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STATE_ACCESS: if(InvalidateCache) NextState = STATE_ACCESS; // exclusion-tag: dcache InvalidateCheck
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else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; // exclusion-tag: icache FLUSHStatement
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else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement
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else if((AnyMiss | CMOWriteback) & ~READ_ONLY_CACHE) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
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else NextState = STATE_HIT;
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else NextState = STATE_ACCESS;
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STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
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else NextState = STATE_FETCH;
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STATE_WRITE_LINE: NextState = STATE_ADDRESS_SETUP;
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STATE_ADDRESS_SETUP: if(Stall) NextState = STATE_ADDRESS_SETUP;
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else NextState = STATE_HIT;
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else NextState = STATE_ACCESS;
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// exclusion-tag-start: icache case
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STATE_WRITEBACK: if(CacheBusAck & ~(|CMOpM[3:1])) NextState = STATE_FETCH;
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else if(CacheBusAck) NextState = STATE_ADDRESS_SETUP; // Read_hold lowers CacheStall
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@ -138,14 +138,14 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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else if(CacheBusAck) NextState = STATE_ADDRESS_SETUP;
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else NextState = STATE_FLUSH_WRITEBACK;
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// exclusion-tag-end: icache case
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default: NextState = STATE_HIT;
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default: NextState = STATE_ACCESS;
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endcase
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end
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// com back to CPU
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assign CacheCommitted = (CurrState != STATE_HIT) & ~(READ_ONLY_CACHE & (CurrState == STATE_ADDRESS_SETUP));
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assign CacheCommitted = (CurrState != STATE_ACCESS) & ~(READ_ONLY_CACHE & (CurrState == STATE_ADDRESS_SETUP));
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assign StallConditions = FlushCache | AnyMiss | CMOWriteback; // exclusion-tag: icache FlushCache
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assign CacheStall = (CurrState == STATE_HIT & StallConditions) | // exclusion-tag: icache StallStates
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assign CacheStall = (CurrState == STATE_ACCESS & StallConditions) | // exclusion-tag: icache StallStates
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(CurrState == STATE_FETCH) |
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(CurrState == STATE_WRITEBACK) |
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(CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
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@ -153,15 +153,15 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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(CurrState == STATE_FLUSH_WRITEBACK);
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// write enables internal to cache
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assign SetValid = CurrState == STATE_WRITE_LINE |
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(CurrState == STATE_HIT & CMOZeroNoEviction) |
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(CurrState == STATE_ACCESS & CMOZeroNoEviction) |
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(CurrState == STATE_WRITEBACK & CacheBusAck & CMOpM[3]);
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assign ClearValid = (CurrState == STATE_HIT & CMOpM[0]) |
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assign ClearValid = (CurrState == STATE_ACCESS & CMOpM[0]) |
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(CurrState == STATE_WRITEBACK & CMOpM[2] & CacheBusAck);
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assign LRUWriteEn = (((CurrState == STATE_HIT & (AnyHit | CMOZeroNoEviction)) |
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assign LRUWriteEn = (((CurrState == STATE_ACCESS & (AnyHit | CMOZeroNoEviction)) |
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(CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
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(CurrState == STATE_WRITEBACK & CMOpM[3] & CacheBusAck);
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// exclusion-tag-start: icache flushdirtycontrols
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assign SetDirty = (CurrState == STATE_HIT & (AnyUpdateHit | CMOZeroNoEviction)) | // exclusion-tag: icache SetDirty
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assign SetDirty = (CurrState == STATE_ACCESS & (AnyUpdateHit | CMOZeroNoEviction)) | // exclusion-tag: icache SetDirty
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(CurrState == STATE_WRITE_LINE & (CacheRW[0])) |
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(CurrState == STATE_WRITEBACK & (CMOpM[3] & CacheBusAck));
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assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty
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@ -169,10 +169,10 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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// Flush and eviction controls
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CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2]) & CacheBusAck;
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assign SelVictim = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOpM[1] | CMOpM[2])) | (CacheBusAck & CMOpM[3]))) |
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(CurrState == STATE_HIT & ((AnyMiss & LineDirty) | (CMOZeroNoEviction & ~CacheHit))) |
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(CurrState == STATE_ACCESS & ((AnyMiss & LineDirty) | (CMOZeroNoEviction & ~CacheHit))) |
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(CurrState == STATE_WRITE_LINE);
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assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2] | ~CacheBusAck)) |
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(CurrState == STATE_HIT & AnyMiss & LineDirty);
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(CurrState == STATE_ACCESS & AnyMiss & LineDirty);
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// coverage off -item e 1 -fecexprrow 1
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// (state is always FLUSH_WRITEBACK when FlushWayFlag & CacheBusAck)
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
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@ -183,29 +183,29 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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(CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck);
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// exclusion-tag-end: icache flushdirtycontrols
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// Bus interface controls
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assign CacheBusRW[1] = (CurrState == STATE_HIT & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses
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assign CacheBusRW[1] = (CurrState == STATE_ACCESS & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses
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(CurrState == STATE_FETCH & ~CacheBusAck) |
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(CurrState == STATE_WRITEBACK & CacheBusAck & ~(|CMOpM));
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logic LoadMiss;
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assign LoadMiss = (CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
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assign CacheBusRW[0] = (CurrState == STATE_HIT & LoadMiss & LineDirty) | // exclusion-tag: icache CacheBusW
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assign CacheBusRW[0] = (CurrState == STATE_ACCESS & LoadMiss & LineDirty) | // exclusion-tag: icache CacheBusW
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(CurrState == STATE_WRITEBACK & ~CacheBusAck) |
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(CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck) |
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(CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2]) & ~CacheBusAck);
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assign SelAdrData = (CurrState == STATE_HIT & (CacheRW[0] | AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
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assign SelAdrData = (CurrState == STATE_ACCESS & (CacheRW[0] | AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
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(CurrState == STATE_FETCH) |
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(CurrState == STATE_WRITEBACK) |
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(CurrState == STATE_WRITE_LINE) |
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resetDelay;
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assign SelAdrTag = (CurrState == STATE_HIT & (AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrTag // changes if store delay hazard removed
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assign SelAdrTag = (CurrState == STATE_ACCESS & (AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrTag // changes if store delay hazard removed
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(CurrState == STATE_FETCH) |
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(CurrState == STATE_WRITEBACK) |
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(CurrState == STATE_WRITE_LINE) |
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resetDelay;
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assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_ADDRESS_SETUP;
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assign CacheEn = (~Stall | StallConditions) | (CurrState != STATE_HIT) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn
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assign CacheEn = (~Stall | StallConditions) | (CurrState != STATE_ACCESS) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn
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endmodule // cachefsm
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