UM comments in fdivsqrtotfc

src/fpu/fdivsqrt/fdivsqrt.sv

@@ -41,14 +41,14 @@ module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
   input  logic                 StallM,
   input  logic                 FlushE,
   input  logic                 SqrtE, SqrtM,
-  input  logic [P.XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+  input  logic [P.XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // these are the src A/B outputs before the mux choosing between them and PCE to put in srcA/B
   input  logic [2:0]           Funct3E, Funct3M,
   input  logic                 IntDivE, W64E,
   output logic                 DivStickyM,
   output logic                 FDivBusyE, IFDivStartE, FDivDoneE,
   output logic [P.NE+1:0]      UeM,                         // Exponent result 
   output logic [P.DIVb:0]      UmM,                         // Significand result
-  output logic [P.XLEN-1:0]    FIntDivResultM
+  output logic [P.XLEN-1:0]    FIntDivResultM               // Integer division result (IntDivResult in figure)
 );
 
   // Floating-point division and square root module, with optional integer division and remainder

src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -33,7 +33,7 @@
 module fdivsqrtuotfc2 import cvw::*;  #(parameter cvw_t P) (
   input  logic             up, un,
   input  logic [P.DIVb+1:0] C,                // Q2.DIVb
-  input  logic [P.DIVb:0]   U, UM,            // U1.DIVb
+  input  logic [P.DIVb:0]   U, UM,            // U1.DIVb  UM is actually U - 1 ulp and starts negative, but this representation still produces the right answer
   output logic [P.DIVb:0]   UNext, UMNext     // U1.DIVb
 );
   //  The on-the-fly converter transfers the divsqrt

src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -29,7 +29,7 @@
 
 module fdivsqrtuotfc4 import cvw::*;  #(parameter cvw_t P) (
   input  logic [3:0]     udigit,
-  input  logic [P.DIVb:0] U, UM,          // U1.DIVb
+  input  logic [P.DIVb:0] U, UM,          // U1.DIVb  UM is actually U - 1 ulp and starts negative, but this representation still produces the right answer
   input  logic [P.DIVb:0] C,              // Q1.DIVb
   output logic [P.DIVb:0] UNext, UMNext   // U1.DIVb
 );