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Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.
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Rose Thompson
parent
4c3d927474
commit
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@ -423,7 +423,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(MISALIGN_SUPPORT) begin
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subwordreadmisaligned #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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//subwordreadmisaligned #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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subwordwritemisaligned #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM);
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end else begin
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196
src/lsu/subwordreaddouble.sv
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196
src/lsu/subwordreaddouble.sv
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@ -0,0 +1,196 @@
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///////////////////////////////////////////
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// subwordread.sv
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//
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// Written: David_Harris@hmc.edu
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// Created: 9 January 2021
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// Modified: 18 January 2023
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//
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// Purpose: Extract subwords and sign extend for reads
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module subwordreaddouble #(parameter LLEN)
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(
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input logic [LLEN*2-1:0] ReadDataWordMuxM,
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input logic [2:0] PAdrM,
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input logic [2:0] Funct3M,
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input logic FpLoadStoreM,
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input logic BigEndianM,
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output logic [LLEN-1:0] ReadDataM
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);
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logic [7:0] ByteM;
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logic [15:0] HalfwordM;
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logic [4:0] PAdrSwap;
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logic [4:0] BigEndianPAdr;
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logic [4:0] LengthM;
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// Funct3M[2] is the unsigned bit. mask upper bits.
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// Funct3M[1:0] is the size of the memory access.
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assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
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/* verilator lint_off WIDTHEXPAND */
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/* verilator lint_off WIDTHTRUNC */
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assign BigEndianPAdr = (LLEN/4) - PAdrM - LengthM;
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/* verilator lint_on WIDTHTRUNC */
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/* verilator lint_on WIDTHEXPAND */
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always_comb
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case(Funct3M & {FpLoadStoreM, 2'b11})
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3'b000: LengthM = 5'd1;
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3'b001: LengthM = 5'd2;
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3'b010: LengthM = 5'd4;
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3'b011: LengthM = 5'd8;
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3'b100: LengthM = 5'd16;
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default: LengthM = 5'd8;
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endcase
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if (LLEN == 128) begin:swrmux
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logic [31:0] WordM;
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logic [63:0] DblWordM;
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logic [63:0] QdWordM;
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always_comb
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case(PAdrSwap)
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5'b00000: QdWordM = ReadDataWordMuxM[127:0];
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5'b00001: QdWordM = ReadDataWordMuxM[135:8];
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5'b00010: QdWordM = ReadDataWordMuxM[143:16];
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5'b00011: QdWordM = ReadDataWordMuxM[151:24];
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5'b00100: QdWordM = ReadDataWordMuxM[159:32];
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5'b00101: QdWordM = ReadDataWordMuxM[167:40];
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5'b00110: QdWordM = ReadDataWordMuxM[175:48];
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5'b00111: QdWordM = ReadDataWordMuxM[183:56];
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5'b01000: QdWordM = ReadDataWordMuxM[191:64];
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5'b01001: QdWordM = ReadDataWordMuxM[199:72];
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5'b01010: QdWordM = ReadDataWordMuxM[207:80];
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5'b01011: QdWordM = ReadDataWordMuxM[215:88];
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5'b01100: QdWordM = ReadDataWordMuxM[223:96];
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5'b01101: QdWordM = ReadDataWordMuxM[231:104];
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5'b01110: QdWordM = ReadDataWordMuxM[239:112];
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5'b01111: QdWordM = ReadDataWordMuxM[247:120];
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5'b10000: QdWordM = ReadDataWordMuxM[255:128];
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5'b10001: QdWordM = {8'b0, ReadDataWordMuxM[255:136]};
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5'b10010: QdWordM = {16'b0, ReadDataWordMuxM[255:144]};
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5'b10011: QdWordM = {24'b0, ReadDataWordMuxM[255:152]};
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5'b10100: QdWordM = {32'b0, ReadDataWordMuxM[255:160]};
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5'b10101: QdWordM = {40'b0, ReadDataWordMuxM[255:168]};
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5'b10110: QdWordM = {48'b0, ReadDataWordMuxM[255:176]};
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5'b10111: QdWordM = {56'b0, ReadDataWordMuxM[255:184]};
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5'b11000: QdWordM = {64'b0, ReadDataWordMuxM[255:192]};
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5'b11001: QdWordM = {72'b0, ReadDataWordMuxM[255:200]};
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5'b11010: QdWordM = {80'b0, ReadDataWordMuxM[255:208]};
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5'b11011: QdWordM = {88'b0, ReadDataWordMuxM[255:216]};
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5'b11100: QdWordM = {96'b0, ReadDataWordMuxM[255:224]};
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5'b11101: QdWordM = {104'b0, ReadDataWordMuxM[255:232]};
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5'b11110: QdWordM = {112'b0, ReadDataWordMuxM[255:240]};
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5'b11111: QdWordM = {120'b0, ReadDataWordMuxM[255:248]};
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endcase
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assign ByteM = QdWordM[7:0];
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assign HalfwordM = QdWordM[15:0];
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assign WordM = QdWordM[31:0];
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assign DblWordM = QdWordM[63:0];
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// sign extension/ NaN boxing
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always_comb
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case(Funct3M)
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3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
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3'b011: ReadDataM = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
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3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
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3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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3'b110: ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]}; // lwu
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default: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // Shouldn't happen
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endcase
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end else if (LLEN == 64) begin:swrmux
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logic [31:0] WordM;
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logic [63:0] DblWordM;
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: DblWordM = ReadDataWordMuxM[63:0];
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4'b0001: DblWordM = ReadDataWordMuxM[71:8];
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4'b0010: DblWordM = ReadDataWordMuxM[79:16];
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4'b0011: DblWordM = ReadDataWordMuxM[87:24];
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4'b0100: DblWordM = ReadDataWordMuxM[95:32];
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4'b0101: DblWordM = ReadDataWordMuxM[103:40];
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4'b0110: DblWordM = ReadDataWordMuxM[111:48];
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4'b0111: DblWordM = ReadDataWordMuxM[119:56];
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4'b1000: DblWordM = ReadDataWordMuxM[127:64];
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4'b1001: DblWordM = {8'b0, ReadDataWordMuxM[127:72]};
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4'b1010: DblWordM = {16'b0, ReadDataWordMuxM[127:80]};
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4'b1011: DblWordM = {24'b0, ReadDataWordMuxM[127:88]};
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4'b1100: DblWordM = {32'b0, ReadDataWordMuxM[127:96]};
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4'b1101: DblWordM = {40'b0, ReadDataWordMuxM[127:104]};
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4'b1110: DblWordM = {48'b0, ReadDataWordMuxM[127:112]};
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4'b1111: DblWordM = {56'b0, ReadDataWordMuxM[127:120]};
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endcase
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assign ByteM = DblWordM[7:0];
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assign HalfwordM = DblWordM[15:0];
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assign WordM = DblWordM[31:0];
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// sign extension/ NaN boxing
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always_comb
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case(Funct3M)
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3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
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3'b011: ReadDataM = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
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3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
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3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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3'b110: ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]}; // lwu
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default: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // Shouldn't happen
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endcase
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end else begin:swrmux // 32-bit
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logic [31:0] WordM;
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always_comb
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case(PAdrSwap[2:0])
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3'b000: WordM = ReadDataWordMuxM[31:0];
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3'b001: WordM = ReadDataWordMuxM[39:8];
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3'b010: WordM = ReadDataWordMuxM[47:16];
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3'b011: WordM = ReadDataWordMuxM[55:24];
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3'b100: WordM = ReadDataWordMuxM[63:32];
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3'b101: WordM = {8'b0, ReadDataWordMuxM[63:40]};
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3'b110: WordM = {16'b0, ReadDataWordMuxM[63:48]};
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3'b111: WordM = {24'b0, ReadDataWordMuxM[63:56]};
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endcase
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assign ByteM = WordM[7:0];
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assign HalfwordM = WordM[15:0];
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// sign extension
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always_comb
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case(Funct3M)
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3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw
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3'b011: ReadDataM = ReadDataWordMuxM[LLEN-1:0]; // fld
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3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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default: ReadDataM = ReadDataWordMuxM[LLEN-1:0]; // Shouldn't happen
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endcase
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end
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endmodule
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