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removed j1,j0 from iteration and put inside divider stage

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Kevin Kim 2024-03-04 14:30:05 -08:00
parent 7dec9cdf21
commit 587fdbdf8e
2 changed files with 5 additions and 5 deletions
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5
src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -107,10 +107,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
end else begin: stage
logic j1,j0;
assign j0 = (i == 0 & ~C[0][P.DIVb+1]);
assign j1 = (i == 1 & ~C[0][P.DIVb+1]) || (i == 0 & (C[0][P.DIVb-1] ^ C[0][P.DIVb]));
fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .j0,
fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE,
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
end

5
src/fpu/fdivsqrt/fdivsqrtstage4.sv
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@ -32,7 +32,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) (
input logic [P.DIVb:0] U,UM, // U1.DIVb
input logic [P.DIVb+3:0] WS, WC, // Q4.DIVb
input logic [P.DIVb+1:0] C, // Q2.DIVb
input logic SqrtE, j1,j0,
input logic SqrtE,
output logic [P.DIVb+1:0] CNext, // Q2.DIVb
output logic un,
output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb
@ -48,8 +48,11 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) (
logic [7:0] WCmsbs, WSmsbs; // U4.4
logic CarryIn;
logic [P.DIVb+3:0] WSA, WCA; // Q4.DIVb
logic j0,j1;
// Digit Selection logic
assign j0 = ~C[P.DIVb+1]; // first step of R digit selection: C = 00...0
assign j1 = C[P.DIVb] ^ C[P.DIVb-1]; // second step of R digit selection: C = 1100...0
assign Smsbs = U[P.DIVb:P.DIVb-4]; // U1.4 most significant bits of square root
assign Dmsbs = D[P.DIVb-1:P.DIVb-3]; // U0.3 most significant fractional bits of divisor after leading 1
assign WCmsbs = WC[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual