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AES cleanup
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@ -32,13 +32,13 @@ module aes64d(
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output logic [63:0] result
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);
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logic [63:0] ShiftRowOut, SboxOut, MixcolIn, MixcolOut;
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logic [63:0] ShiftRowsOut, SboxOut, MixcolIn, MixcolOut;
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// Apply inverse shiftrows to rs2 and rs1
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aesinvshiftrow64 srow({rs2, rs1}, ShiftRowOut);
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aesinvshiftrows64 srow({rs2, rs1}, ShiftRowsOut);
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// Apply full word inverse substitution to lower doubleord of shiftrow out
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aesinvsbox64 invsbox(ShiftRowOut, SboxOut);
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aesinvsbox64 invsbox(ShiftRowsOut, SboxOut);
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mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn);
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@ -34,17 +34,17 @@ module aes64e(
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output logic [63:0] result
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);
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logic [63:0] ShiftRowOut, SboxOut, MixcolOut;
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logic [63:0] ShiftRowsOut, SboxOut, MixcolOut;
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// AES shiftrow unit
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aesshiftrow64 srow({rs2,rs1}, ShiftRowOut);
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aesshiftrows64 srow({rs2,rs1}, ShiftRowsOut);
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// Apply substitution box to 2 lower words
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// Use the shared sbox in zknde64.sv for the first sbox
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assign SboxEIn = ShiftRowOut[31:0];
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assign SboxEIn = ShiftRowsOut[31:0];
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assign SboxOut[31:0] = Sbox0Out;
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aessbox32 sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox
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aessbox32 sbox1(ShiftRowsOut[63:32], SboxOut[63:32]); // instantiate second sbox
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// Apply MixColumns operations
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aesmixcolumns32 mw0(SboxOut[31:0], MixcolOut[31:0]);
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// aesinvshiftrow.sv
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// aesinvshiftrows64.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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@ -25,9 +25,9 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aesinvshiftrow64(
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module aesinvshiftrows64(
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input logic [127:0] a,
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output logic [63:0] y
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output logic [63:0] y
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);
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assign y = {a[95:88], a[119:112], a[15:8], a[39:32],
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// aesshiftrow.sv
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// aesshiftrows64.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aesshiftrow64(
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module aesshiftrows64(
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input logic [127:0] a,
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output logic [63:0] y
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);
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35
src/ieu/aes/aesshiftrows64.xv
Normal file
35
src/ieu/aes/aesshiftrows64.xv
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@ -0,0 +1,35 @@
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///////////////////////////////////////////
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// aesshiftrows64.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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//
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// Purpose: aesshiftrow for taking in first Data line
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aesshiftrows64(
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input logic [127:0] a,
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output logic [63:0] y
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);
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assign y = {a[31:24], a[119:112], a[79:72], a[39:32],
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a[127:120], a[87:80], a[47:40], a[7:0]};
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endmodule
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