mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
This commit is contained in:
David Harris
commit
9c04df8f69
@ -94,7 +94,7 @@ localparam LOGR = $clog2(RADIX); // r = log(R
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localparam RK = LOGR*DIVCOPIES; // r*k bits per cycle generated
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// intermediate division parameters not directly used in fdivsqrt hardware
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localparam FPDIVMINb = NF + 3; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right
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localparam FPDIVMINb = NF + 2; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right
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//localparam FPDIVMINb = NF + 2 + (RADIX == 2); // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit for preshifting radix2 square root right, if radix4 doesn't use a right shift. This version saves one cycle on double-precision with R=4,k=4. However, it doesn't work yet because C is too short, so k is incorrectly calculated as a 1 in the lsb after the last step.
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localparam DIVMINb = ((FPDIVMINb<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVMINb; // minimum fractional bits b = max(XLEN, FPDIVMINb)
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localparam RESBITS = DIVMINb + LOGR; // number of bits in a result: r integer + b fractional
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@ -33,6 +33,7 @@ os.chdir(regressionDir)
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coverage = '-coverage' in sys.argv
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fp = '-fp' in sys.argv
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nightly = '-nightly' in sys.argv
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softfloat = '-softfloat' in sys.argv
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TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
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# name: the name of this test configuration (used in printing human-readable
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@ -267,18 +268,17 @@ if (nightly):
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["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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# enable floating-point tests when lint is fixed
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# ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
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# ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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# ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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# ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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# ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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# ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
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# ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
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# ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
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# ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
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# ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
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["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
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["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
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["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
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["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
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["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
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["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
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]
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@ -309,6 +309,87 @@ for test in tests32e:
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grepstr="All tests ran without failures")
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configs.append(tc)
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# softfloat tests
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if (softfloat):
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configs = []
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softfloatconfigs = ['fdh_ieee_rv32gc', 'fdqh_ieee_rv32gc', 'fdq_ieee_rv32gc', \
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'fh_ieee_v32gc', 'f_ieee_rv64gc', 'fdqh_ieee_rv64gc', \
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'fdq_ieee_rv64gc', 'div_2_1_rv32gc', 'div_2_2_rv32gc', \
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'div_2_4_rv32gc', 'div_4_1_rv32gc', 'div_4_2_rv32gc', \
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'div_4_4_rv32gc', 'fd_ieee_rv32gc', 'fh_ieee_rv32gc', \
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'div_2_1_rv64gc', 'div_2_2_rv64gc', 'div_2_4_rv64gc', \
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'div_4_1_rv64gc', 'div_4_2_rv64gc', 'div_4_4_rv64gc', \
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'fd_ieee_rv64gc', 'fh_ieee_rv64gc', 'f_ieee_rv32gc']
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softfloatconfigs = ['fdh_ieee_div_2_1_rv32gc', 'fdh_ieee_div_2_1_rv64gc', \
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'fdh_ieee_div_2_2_rv32gc', 'fdh_ieee_div_2_2_rv64gc', 'fdh_ieee_div_2_4_rv32gc', \
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'fdh_ieee_div_2_4_rv64gc', 'fdh_ieee_div_4_1_rv32gc', 'fdh_ieee_div_4_1_rv64gc', \
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'fdh_ieee_div_4_2_rv32gc', 'fdh_ieee_div_4_2_rv64gc', 'fdh_ieee_div_4_4_rv64gc', \
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'fdh_ieee_rv32gc', 'fd_ieee_div_2_1_rv32gc', 'fd_ieee_div_2_1_rv64gc', \
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'fd_ieee_div_2_2_rv32gc', 'fd_ieee_div_2_2_rv64gc', 'fd_ieee_div_2_4_rv32gc', \
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'fd_ieee_div_2_4_rv64gc', 'fd_ieee_div_4_1_rv32gc', 'fd_ieee_div_4_1_rv64gc', \
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'fd_ieee_div_4_2_rv32gc', 'fd_ieee_div_4_2_rv64gc', 'fd_ieee_div_4_4_rv64gc', \
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'fd_ieee_rv32gc', 'fd_ieee_rv64gc', 'fdqh_ieee_div_2_1_rv32gc', \
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'fdqh_ieee_div_2_1_rv64gc', 'fdqh_ieee_div_2_2_rv32gc', 'fdqh_ieee_div_2_2_rv64gc', \
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'fdqh_ieee_div_2_4_rv32gc', 'fdqh_ieee_div_2_4_rv64gc', 'fdqh_ieee_div_4_1_rv32gc', \
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'fdqh_ieee_div_4_1_rv64gc', 'fdqh_ieee_div_4_2_rv32gc', 'fdqh_ieee_div_4_2_rv64gc',\
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'fdqh_ieee_div_4_4_rv64gc', 'fdqh_ieee_rv32gc', 'fdqh_ieee_rv64gc', \
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'fdq_ieee_div_2_1_rv32gc', 'fdq_ieee_div_2_1_rv64gc', 'fdq_ieee_div_2_2_rv32gc',\
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'fdq_ieee_div_2_2_rv64gc', 'fdq_ieee_div_2_4_rv32gc', 'fdq_ieee_div_2_4_rv64gc', \
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'fdq_ieee_div_4_1_rv32gc', 'fdq_ieee_div_4_1_rv64gc', 'fdq_ieee_div_4_2_rv32gc', \
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'fdq_ieee_div_4_2_rv64gc', 'fdq_ieee_div_4_4_rv64gc', 'fdq_ieee_rv32gc', \
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'fdq_ieee_rv64gc', 'fh_ieee_div_2_1_rv32gc', 'fh_ieee_div_2_1_rv64gc', \
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'fh_ieee_div_2_2_rv32gc', 'fh_ieee_div_2_2_rv64gc', 'fh_ieee_div_2_4_rv32gc',\
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'fh_ieee_div_2_4_rv64gc', 'fh_ieee_div_4_1_rv32gc', 'fh_ieee_div_4_1_rv64gc',\
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'fh_ieee_div_4_2_rv32gc', 'fh_ieee_div_4_2_rv64gc', 'fh_ieee_div_4_4_rv64gc', \
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'fh_ieee_rv32gc', 'fh_ieee_rv64gc', 'fh_ieee_v32gc', 'f_ieee_div_2_1_rv32gc', \
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'f_ieee_div_2_1_rv64gc', 'f_ieee_div_2_2_rv32gc', 'f_ieee_div_2_2_rv64gc', \
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'f_ieee_div_2_4_rv32gc', 'f_ieee_div_2_4_rv64gc', 'f_ieee_div_4_1_rv32gc', \
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'f_ieee_div_4_1_rv64gc', 'f_ieee_div_4_2_rv32gc', 'f_ieee_div_4_2_rv64gc', \
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'f_ieee_div_4_4_rv64gc', 'f_ieee_rv32gc', 'f_ieee_rv64gc']
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for config in softfloatconfigs:
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# div test case
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divtest = TestCase(
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name="div",
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variant=config,
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cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " div \n!",
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grepstr="All Tests completed with 0 errors"
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)
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configs.insert(0,divtest)
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# sqrt test case
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sqrttest = TestCase(
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name="sqrt",
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variant=config,
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cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " sqrt \n!",
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grepstr="All Tests completed with 0 errors"
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)
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#configs.append(sqrttest)
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configs.insert(0,sqrttest)
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# skip if divider variant config
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if ("ieee" in config):
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# cvtint test case
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cvtinttest = TestCase(
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name="cvtint",
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variant=config,
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cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtint \n!",
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grepstr="All Tests completed with 0 errors"
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)
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configs.append(cvtinttest)
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# cvtfp test case
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# WILL fail on F_only (refer to spec)
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cvtfptest = TestCase(
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name="cvtfp",
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variant=config,
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cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtfp \n!",
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grepstr="All Tests completed with 0 errors"
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)
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configs.append(cvtfptest)
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import os
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@ -368,6 +449,8 @@ def main():
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elif '-nightly' in sys.argv:
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TIMEOUT_DUR = 60*1440 # 1 day
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configs.append(getBuildrootTC(boot=False))
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elif '-softfloat' in sys.argv:
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TIMEOUT_DUR = 60*60 # seconds
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else:
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TIMEOUT_DUR = 10*60 # seconds
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configs.append(getBuildrootTC(boot=False))
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55
sim/testfloat-batch.do
Normal file
55
sim/testfloat-batch.do
Normal file
@ -0,0 +1,55 @@
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# testfloat-batch.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021; Kevin Kim 2024
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# Go Cowboys!!!!!!
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#
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||||
# Takes 1:10 to run RV64IC tests using gui
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# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
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onbreak {resume}
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# create library
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if [file exists wkdir/work_${1}_${2}] {
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vdel -lib wkdir/work_${1}_${2} -all
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}
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vlib wkdir/work_${1}_${2}
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# c# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# $num = the added words after the call
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697,7033
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# Set WAV variable to avoid having any output to wave (to limit disk space)
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quietly set WAV 0;
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# Determine if nowave argument is provided this removes any output to
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# a wlf or wave window to reduce disk space.
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if {$WAV eq 0} {
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puts "No wave output is selected"
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} else {
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puts "wave output is selected"
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view wave
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add log -recursive /*
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do wave-fpu.do
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}
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# Change TEST_SIZE to only test certain FP width
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# values are QP, DP, SP, HP or all for all tests
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vopt +acc wkdir/work_${1}_${2}.testbenchfp -work wkdir/work_${1}_${2} -G TEST=$2 -G TEST_SIZE="all" -o testbenchopt
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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#-- Run the Simulation
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run -all
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@ -71,8 +71,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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// The datapath produces rk bits per cycle, so Cycles = ceil (ResultBitsE / rk)
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always_comb begin
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if (SqrtE) FPResultBitsE = Nf + 2 + 0; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1
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else FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits
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FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1
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if (P.IDIV_ON_FPU) ResultBitsE = IntDivE ? IntResultBitsE : FPResultBitsE;
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else ResultBitsE = FPResultBitsE;
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@ -72,20 +72,19 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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// UOTFC Result U and UM registers/initialization mux
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// Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 otherwise
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assign initU = {SqrtE, {(P.DIVb){1'b0}}};
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assign initUM = {~SqrtE, {(P.DIVb){1'b0}}};
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assign initU ={(P.DIVb+1){1'b0}};
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assign initUM = {{1'b1}, {(P.DIVb){1'b0}}};
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mux2 #(P.DIVb+1) Umux(UNext[P.DIVCOPIES-1], initU, IFDivStartE, UMux);
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mux2 #(P.DIVb+1) UMmux(UMNext[P.DIVCOPIES-1], initUM, IFDivStartE, UMMux);
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flopen #(P.DIVb+1) UReg(clk, FDivBusyE, UMux, U[0]);
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flopen #(P.DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
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||||
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// C register/initialization mux
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// Initialize C to -1 for sqrt and -R for division
|
||||
logic [1:0] initCUpper;
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if(P.RADIX == 4) begin
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mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, initCUpper);
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assign initCUpper = 2'b00;
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||||
end else begin
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||||
mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper);
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assign initCUpper = 2'b10;
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||||
end
|
||||
|
||||
assign initC = {initCUpper, {P.DIVb{1'b0}}};
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||||
@ -108,9 +107,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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||||
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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||||
end else begin: stage
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||||
logic j1;
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assign j1 = (i == 0 & ~C[0][P.DIVb-1]);
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||||
fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
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||||
fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE,
|
||||
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
|
||||
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
|
||||
end
|
||||
|
||||
@ -174,9 +174,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
logic [P.DIVb:0] PreSqrtX;
|
||||
assign EvenExp = Xe[0] ^ ell[0]; // effective unbiased exponent after normalization is even
|
||||
mux2 #(P.DIVb+1) sqrtxmux(Xnorm, {1'b0, Xnorm[P.DIVb:1]}, EvenExp, PreSqrtX); // X if exponent odd, X/2 if exponent even
|
||||
if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX}; // PreSqrtX - 2 = 2(PreSqrtX/2 - 1)
|
||||
else assign SqrtX = {2'b11, PreSqrtX, 1'b0}; // 2PreSqrtX - 4 = 4(PreSqrtX/2 - 1)
|
||||
mux2 #(P.DIVb+4) sqrtxmux({4'b0,Xnorm[P.DIVb:1]}, {5'b00, Xnorm[P.DIVb:2]}, EvenExp, SqrtX); // X/2 if exponent odd, X/4 if exponent even
|
||||
|
||||
/*
|
||||
// Attempt to optimize radix 4 to use a left shift by 1 or zero initially, followed by no more left shift
|
||||
|
||||
@ -32,7 +32,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.DIVb:0] U,UM, // U1.DIVb
|
||||
input logic [P.DIVb+3:0] WS, WC, // Q4.DIVb
|
||||
input logic [P.DIVb+1:0] C, // Q2.DIVb
|
||||
input logic SqrtE, j1,
|
||||
input logic SqrtE,
|
||||
output logic [P.DIVb+1:0] CNext, // Q2.DIVb
|
||||
output logic un,
|
||||
output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb
|
||||
@ -48,13 +48,16 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) (
|
||||
logic [7:0] WCmsbs, WSmsbs; // U4.4
|
||||
logic CarryIn;
|
||||
logic [P.DIVb+3:0] WSA, WCA; // Q4.DIVb
|
||||
logic j0,j1;
|
||||
|
||||
// Digit Selection logic
|
||||
assign j0 = ~C[P.DIVb+1]; // first step of R digit selection: C = 00...0
|
||||
assign j1 = C[P.DIVb] ^ C[P.DIVb-1]; // second step of R digit selection: C = 1100...0
|
||||
assign Smsbs = U[P.DIVb:P.DIVb-4]; // U1.4 most significant bits of square root
|
||||
assign Dmsbs = D[P.DIVb-1:P.DIVb-3]; // U0.3 most significant fractional bits of divisor after leading 1
|
||||
assign WCmsbs = WC[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual
|
||||
assign WSmsbs = WS[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual
|
||||
fdivsqrtuslc4cmp uslc4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit);
|
||||
fdivsqrtuslc4cmp uslc4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .j0, .udigit);
|
||||
assign un = 1'b0; // unused for radix 4
|
||||
|
||||
// F generation logic
|
||||
|
||||
@ -31,7 +31,8 @@ module fdivsqrtuslc4cmp (
|
||||
input logic [2:0] Dmsbs, // U0.3 fractional bits after implicit leading 1
|
||||
input logic [4:0] Smsbs, // U1.4 leading bits of square root approximation
|
||||
input logic [7:0] WSmsbs, WCmsbs, // Q4.4 residual most significant bits
|
||||
input logic SqrtE, j1,
|
||||
input logic SqrtE,
|
||||
input logic j0,j1, // are we on first (j0) or second step (j1) of digit selection
|
||||
output logic [3:0] udigit // {2, 1, -1, -2} digit is 0 if none are hot
|
||||
);
|
||||
logic [6:0] Wmsbs;
|
||||
@ -46,7 +47,9 @@ module fdivsqrtuslc4cmp (
|
||||
// Wmsbs = | |
|
||||
|
||||
logic [6:0] mk2, mk1, mk0, mkm1;
|
||||
logic [6:0] mkj2, mkj1, mkj0, mkjm1;
|
||||
logic [6:0] mks2[7:0], mks1[7:0];
|
||||
logic sqrtspecial;
|
||||
|
||||
// Prepopulate table of mks0
|
||||
assign mks2[0] = 12;
|
||||
@ -65,20 +68,26 @@ module fdivsqrtuslc4cmp (
|
||||
assign mks1[5] = 8; // is the logic any cheaper if this is a 6?
|
||||
assign mks1[6] = 8;
|
||||
assign mks1[7] = 8;
|
||||
|
||||
// handles special case when j = 0 or j = 1 for sqrt
|
||||
assign mkj2 = 20; // when j = 1 use mk2[101] when j = 0 use anything bigger than 7.
|
||||
assign mkj1 = j1 ? 8 : 0; // when j = 1 use mk1[101] = 8 and when j = 0 use 0 so we choose u_0 = 1
|
||||
assign sqrtspecial = SqrtE & (j1 | j0);
|
||||
|
||||
// Choose A for current operation
|
||||
// Choose A for current operation
|
||||
always_comb
|
||||
if (SqrtE) begin
|
||||
if (j1) A = 3'b101;
|
||||
else if (Smsbs == 5'b10000) A = 3'b111;
|
||||
if (Smsbs[4]) A = 3'b111; // *** can we get rid of SMSBs case?
|
||||
else A = Smsbs[2:0];
|
||||
end else A = Dmsbs;
|
||||
|
||||
|
||||
// Choose selection constants based on a
|
||||
assign mk2 = mks2[A];
|
||||
assign mk1 = mks1[A];
|
||||
assign mk0 = -mks1[A];
|
||||
assign mkm1 = (A == 3'b000) ? -13 : -mks2[A]; // asymmetry in table
|
||||
|
||||
assign mk2 = sqrtspecial ? mkj2 : mks2[A];
|
||||
assign mk1 = sqrtspecial ? mkj1 : mks1[A];
|
||||
assign mk0 = -mk1;
|
||||
assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide?
|
||||
|
||||
// Compare residual W to selection constants to choose digit
|
||||
always_comb
|
||||
|
||||
@ -51,7 +51,8 @@ configs: $(CONFIG)
|
||||
$(CONFIG):
|
||||
@echo $(CONFIG)
|
||||
cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
|
||||
cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
|
||||
# cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
|
||||
cp -r $(OLDCONFIGDIR)/deriv/$(CONFIG)/* $(CONFIGDIR)
|
||||
|
||||
# adjust DTIM and IROM to reasonable values depending on config
|
||||
ifneq ($(filter $(CONFIG), $(DIRS32)),)
|
||||
@ -61,8 +62,8 @@ else ifneq ($(filter $(CONFIG), $(DIRS64)),)
|
||||
sed -i "s/DTIM_RANGE.*/DTIM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
sed -i "s/IROM_RANGE.*/IROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
|
||||
else
|
||||
$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
|
||||
@echo "Config not in list, RAM_RANGE will be unmodified"
|
||||
$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
|
||||
@echo "Config not in list, RAM_RANGE will be unmodified"
|
||||
endif
|
||||
|
||||
# if USESRAM = 1, set that in the config file, otherwise reduce sizes
|
||||
|
||||
Loading…
Reference in New Issue
Block a user