mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 02:05:21 +00:00
Combined ZBC and ZBKC into one unit
This commit is contained in:
KelvinTr
parent
88d93b31b5
commit
e40ae126d3
@ -88,7 +88,7 @@ for test in tests64i:
|
||||
configs.append(tc)
|
||||
|
||||
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
|
||||
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad",
|
||||
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad",
|
||||
#tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"]
|
||||
for test in tests32gc:
|
||||
tc = TestCase(
|
||||
|
||||
@ -88,8 +88,8 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
|
||||
bitreverse #(P.XLEN) brA(.A(ABMU), .RevA);
|
||||
end
|
||||
|
||||
// ZBC Unit
|
||||
if (P.ZBC_SUPPORTED) begin: zbc
|
||||
// ZBC and ZBKCUnit
|
||||
if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc
|
||||
zbc #(P.XLEN) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
|
||||
end else assign ZBCResult = 0;
|
||||
|
||||
@ -102,11 +102,6 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
|
||||
if (P.ZBKB_SUPPORTED) begin: zbkb
|
||||
zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
|
||||
end else assign ZBKBResult = 0;
|
||||
|
||||
// ZBKC Unit
|
||||
if (P.ZBKC_SUPPORTED) begin: zbkc
|
||||
zbkc #(P.XLEN) ZBKC(.A(ABMU), .B(BBMU), .ZBKCSelect(ZBBSelect[0]), .ZBKCResult);
|
||||
end else assign ZBKCResult = 0;
|
||||
|
||||
// ZBKX Unit
|
||||
if (P.ZBKX_SUPPORTED) begin: zbkx
|
||||
@ -146,14 +141,13 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
|
||||
// Result Select Mux
|
||||
always_comb
|
||||
case (BSelect)
|
||||
// 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC, 0100: ZBKB, 0101: ZBKC, 0110: ZBKX
|
||||
// 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC/ZBKC, 0100: ZBKB, 0110: ZBKX
|
||||
// 0111: ZKND, 1000: ZKNE, 1001: ZKNH, 1010: ZKSED, 1011: ZKSH...
|
||||
4'b0000: ALUResult = PreALUResult;
|
||||
4'b0001: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word.
|
||||
4'b0010: ALUResult = ZBBResult;
|
||||
4'b0011: ALUResult = ZBCResult;
|
||||
4'b0100: ALUResult = ZBKBResult;
|
||||
4'b0101: ALUResult = ZBKCResult;
|
||||
4'b0110: ALUResult = ZBKXResult;
|
||||
4'b0111: ALUResult = ZKNDResult;
|
||||
4'b1000: ALUResult = ZKNEResult;
|
||||
|
||||
@ -91,6 +91,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
|
||||
17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_0001_0000_1_1_1_1_0_0_0_0_0; // slli.uw
|
||||
endcase
|
||||
end
|
||||
|
||||
if (P.ZBB_SUPPORTED) begin
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010))
|
||||
@ -119,10 +120,19 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
|
||||
BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_1_1_0_0_0_0_0; // count word instruction
|
||||
endcase
|
||||
end
|
||||
|
||||
if (P.ZBC_SUPPORTED)
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulr
|
||||
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // ZBC instruction
|
||||
endcase
|
||||
if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin // ZBKC
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul
|
||||
17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulh
|
||||
endcase
|
||||
end
|
||||
|
||||
if (P.ZBS_SUPPORTED) begin // ZBS
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_1_1_0_1_0_0; // bclr
|
||||
@ -172,7 +182,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
|
||||
17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0101_1_0_1_1_0_0_0_0_0; //packw
|
||||
endcase
|
||||
end
|
||||
|
||||
if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin // ZBB and ZBKB shared instructions
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // rol
|
||||
@ -196,13 +205,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
|
||||
endcase
|
||||
end
|
||||
|
||||
if (P.ZBKC_SUPPORTED) begin // ZBKC
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0101_0000_1_0_0_1_0_0_0_0_0; // clmul
|
||||
17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0101_0001_1_0_0_1_0_0_0_0_0; // clmulh
|
||||
endcase
|
||||
end
|
||||
|
||||
if (P.ZBKX_SUPPORTED) begin //ZBKX
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0010100_100: BMUControlsD = `BMUCTRLW'b000_0110_0000_1_0_0_1_0_0_0_0_0; // xperm8
|
||||
|
||||
@ -1,55 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// zbkc.sv
|
||||
//
|
||||
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
|
||||
// Created: 27 November 2023
|
||||
//
|
||||
// Purpose: RISC-V ZBKC top level unit
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
// https://github.com/openhwgroup/cvw
|
||||
//
|
||||
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module zbkc #(parameter WIDTH=32)
|
||||
(input logic [WIDTH-1:0] A, B,
|
||||
input logic ZBKCSelect,
|
||||
output logic [WIDTH-1:0] ZBKCResult);
|
||||
|
||||
logic [WIDTH-1:0] temp, if_temp;
|
||||
integer i;
|
||||
|
||||
always_comb begin
|
||||
temp = 0;
|
||||
if (ZBKCSelect != 1'b0) begin // clmulh
|
||||
for (i=1; i<WIDTH; i+=1) begin: clmulh
|
||||
if_temp = (B >> i) & 1;
|
||||
if(if_temp[0]) temp = temp ^ (A >> (WIDTH-i));
|
||||
else temp = temp;
|
||||
end
|
||||
end
|
||||
else begin // clmul
|
||||
for (i=0; i<WIDTH; i+=1) begin: clmul
|
||||
if_temp = (B >> i) & 1;
|
||||
if(if_temp[0]) temp = temp ^ (A << i);
|
||||
else temp = temp;
|
||||
end
|
||||
end
|
||||
end
|
||||
assign ZBKCResult = temp;
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user