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Non-ideal fix. Added new output from pma which indicates if the write shift should occur.

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The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..
This commit is contained in:
Rose Thompson 2024-02-22 09:14:43 -06:00
parent 6a9c2d8dc4
commit 3714b2bf4a
5 changed files with 13 additions and 10 deletions
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2
src/ifu/ifu.sv
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@ -185,7 +185,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
.TLBFlush,
.PhysicalAddress(PCPF),
.TLBMiss(ITLBMissF),
.Cacheable(CacheableF), .Idempotent(), .SelTIM(SelIROM),
.Cacheable(CacheableF), .Idempotent(), .AllowShift(), .SelTIM(SelIROM),
.InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
.InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
.LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),

5
src/lsu/lsu.sv
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@ -119,6 +119,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic SelSpillE; // Align logic detected a spill and needs to stall
logic CacheableM; // PMA indicates memory address is cacheable
logic AllowShiftM; // PMA: indicates if WriteData should be byte shifted before going to cache or bus by offset.
logic BusCommittedM; // Bus memory operation in flight, delay interrupts
logic DCacheCommittedM; // D$ memory operation started, delay interrupts
@ -244,7 +245,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
.PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .AllowShift(AllowShiftM), .SelTIM(SelDTIM),
.InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM),
.StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM),
.StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
@ -426,7 +427,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if(MISALIGN_SUPPORT) begin
subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .CacheableM, .IMAFWriteDataM, .LittleEndianWriteDataM);
subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM);
end else begin
subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);

6
src/lsu/subwordwritedouble.sv
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@ -33,7 +33,7 @@ module subwordwritedouble #(parameter LLEN) (
input logic [2:0] PAdrM,
input logic FpLoadStoreM,
input logic BigEndianM,
input logic CacheableM,
input logic AllowShiftM,
input logic [LLEN-1:0] IMAFWriteDataM,
output logic [LLEN*2-1:0] LittleEndianWriteDataM
);
@ -48,8 +48,8 @@ module subwordwritedouble #(parameter LLEN) (
// 10: PAdrM[2:0]
// 11: BigEndianPAdr
// 00: 00000
// 01: 00111
mux4 #(5) OffsetMux(5'b0, 5'b11111, {2'b0, PAdrM}, BigEndianPAdr, {CacheableM, BigEndianM}, PAdrSwap);
// 01: 11111
mux4 #(5) OffsetMux(5'b0, 5'b11111, {2'b0, PAdrM}, BigEndianPAdr, {AllowShiftM, BigEndianM}, PAdrSwap);
//assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
/* verilator lint_off WIDTHEXPAND */
/* verilator lint_off WIDTHTRUNC */

3
src/mmu/mmu.sv
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@ -49,6 +49,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
output logic TLBMiss, // Miss TLB
output logic Cacheable, // PMA indicates memory address is cachable
output logic Idempotent, // PMA indicates memory address is idempotent
output logic AllowShift, // PMA indicates if WriteData should be byte shifted before going to cache or bus by offset
output logic SelTIM, // Select a tightly integrated memory
// Faults
output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
@ -112,7 +113,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
pmachecker #(P) pmachecker(.PhysicalAddress, .Size, .CMOpM,
.AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PBMemoryType,
.Cacheable, .Idempotent, .SelTIM,
.Cacheable, .Idempotent, .AllowShift, .SelTIM,
.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
if (P.PMP_ENTRIES > 0) begin : pmp

7
src/mmu/pmachecker.sv
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@ -1,4 +1,4 @@
///////////////////////////////////////////
//////////////////////////////////////////
// pmachecker.sv
//
// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
@ -38,7 +38,7 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
input logic WriteAccessM, // Write access
input logic ReadAccessM, // Read access
input logic [1:0] PBMemoryType, // PBMT field of PTE during TLB hit, or 00 otherwise
output logic Cacheable, Idempotent, SelTIM,
output logic Cacheable, Idempotent, AllowShift, SelTIM,
output logic PMAInstrAccessFaultF,
output logic PMALoadAccessFaultM,
output logic PMAStoreAmoAccessFaultM
@ -60,7 +60,8 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
// Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-cachable
assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0;
assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0;
assign AllowShift = SelRegions[1] | SelRegions[2] | SelRegions[3] | SelRegions[5] | SelRegions[6];
// Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
// I/O is nonidempotent. PBMT can override PMA; NC is idempotent and IO is non-idempotent