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Resolved merge conflict

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This commit is contained in:
David Harris 2024-04-26 16:15:23 -07:00
commit 1274ec55af
4 changed files with 4 additions and 4 deletions
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2
addins/riscv-dv

@ -1 +1 @@
Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172
Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580

2
sim/questa/wally-imperas-cov.do
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@ -50,7 +50,7 @@ vlog +incdir+$env(WALLY)/config/$1 \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
\
$env(WALLY)/src/cvw.sv \
$env(WALLY)/src/cvw.sv \
$env(WALLY)/testbench/testbench-imperas.sv \
$env(WALLY)/testbench/common/*.sv \
$env(WALLY)/src/*/*.sv \

2
site-setup.sh
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@ -11,7 +11,7 @@
# Must edit these based on your local environment.
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4 # Change this for your path to Questa, excluding bin
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin

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src/cache/cachefsm.sv vendored
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@ -102,7 +102,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
// outputs for the performance counters.
assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
assign CacheMiss = CacheAccess & ~Hit;
assign CacheMiss = CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage;
// special case on reset. When the fsm first exists reset twayhe
// PCNextF will no longer be pointing to the correct address.