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https://github.com/openhwgroup/cvw
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More fround stub code to keep VCS happy
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@ -274,6 +274,7 @@ os.chdir(regressionDir)
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coveragesim = "questa" # Questa is required for code/functional coverage
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defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
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#defaultsim = "verilator" # Default simulator for all other tests
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coverage = '--coverage' in sys.argv
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fp = '--fp' in sys.argv
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@ -300,9 +301,9 @@ configs = [
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TestCase(
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name="lints",
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variant="all",
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cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/questa/logs/all_lints.log",
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cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/verilator/logs/all_lints.log",
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grepstr="lints run with no errors or warnings",
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grepfile = WALLY + "/sim/questa/logs/all_lints.log")
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grepfile = WALLY + "/sim/verilator/logs/all_lints.log")
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]
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if (coverage): # only run RV64GC tests on Questa in coverage mode
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@ -162,7 +162,9 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
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logic [P.FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
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logic mvsgn; // sign bit for extending move
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logic [P.FLEN-1:0] FliResE; // Floating-point load immediate value
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logic [P.FLEN-1:0] FliResE; // Zfa Floating-point load immediate value
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logic [P.FLEN-1:0] FRoundE; // Zfa fround output
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logic [4:0] FRoundFlagsE; // Zfa fround flags
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//////////////////////////////////////////////////////////////////////////////////////////
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// Decode Stage: fctrl decoder, read register file
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@ -267,15 +269,25 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
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.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
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// floating-point load immediate: fli
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// ZFA: fround and floating-point load immediate fli
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if (P.ZFA_SUPPORTED) begin
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logic [4:0] Rs1E;
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logic [1:0] Fmt2E; // Two-bit format field from instruction
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// fround
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fround #(P) fround(.Xs(XsE), .Xe(XeE), .Xm(XmE),
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.XNaN(XNaNE), .XSNaN(XSNaNE), .XZero(XZeroE), .Fmt(FmtE),
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.FRound(FRoundE), .FRoundFlags(FRoundFlagsE));
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// fli
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flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E);
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flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E);
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fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE));
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end else assign FliResE = '0;
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end else begin
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assign FRoundE = '0;
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assign FRoundFlagsE = '0;
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assign FliResE = '0;
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end
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// fmv.*.x: NaN Box SrcA to extend integer to requested FP size
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if(P.FPSIZES == 1)
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@ -34,10 +34,11 @@ module fround import cvw::*; #(parameter cvw_t P) (
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input logic XNaN, // X is NaN
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input logic XSNaN, // X is Signalling NaN
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input logic XZero, // X is Zero
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input logic [P.FMTBITS-1:0] Fmt // the input's precision (11=quad 01=double 00=single 10=half)
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input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half)
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output logic [P.FLEN-1:0] FRound, // Rounded result
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output logic [4:0] FRoundFlags // Rounder flags
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);
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logic [P.NE-2:0] Bias;
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logic [P.NE-1:0] E;
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logic [P.NF:0] Imask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd;
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@ -171,4 +172,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
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assign Inexact = FRoundNX & ~(XNaN | Exact) & (Rp | T');
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*/
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assign FRound = '0;
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assign FRoundFlags = '0;
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endmodule
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