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ROM preload compatible with Verilator lint, sim, and Design Compiler

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This commit is contained in:
David Harris 2024-04-24 08:44:37 -07:00
parent 3950588b8c
commit 235a3dcfca
1 changed files with 13 additions and 8 deletions
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21
src/generic/mem/rom1p1r.sv
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@ -33,12 +33,6 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
output logic [DATA_WIDTH-1:0] dout
);
`ifdef VERILATOR
import "DPI-C" function string getenvval(input string env_name);
string WALLY_DIR = getenvval("WALLY");
`else
string WALLY_DIR = "$WALLY";
`endif
// Core Memory
bit [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
@ -53,10 +47,21 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
end else begin */
`ifdef VERILATOR
import "DPI-C" function string getenvval(input string env_name);
`endif
initial
if (PRELOAD_ENABLED) begin
if (DATA_WIDTH == 64) $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0); // load boot ROM for FPGA
else begin // put something in the ROM so it is not optimized away
if (DATA_WIDTH == 64) begin
`ifdef VERILATOR
// because Verilator doesn't automatically accept $WALLY from shell
string WALLY_DIR = getenvval("WALLY");
$readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0); // load boot ROM for FPGA
`else
$readmemh({"$WALLY/fpga/src/boot.mem"}, ROM, 0); // load boot ROM for FPGA
`endif
end else begin // put something in the ROM so it is not optimized away
ROM[0] = 'h00002197;
end
end