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changed U/C initialization to account for integer bit generation on divider stage for sqrt. Quick and dirty j1 logic fix

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Kevin Kim 2024-03-03 10:30:18 -08:00
parent 6c24afaf98
commit c32173f163
1 changed files with 4 additions and 4 deletions
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8
src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -72,8 +72,8 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
// UOTFC Result U and UM registers/initialization mux
// Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 otherwise
assign initU = {SqrtE, {(P.DIVb){1'b0}}};
assign initUM = {~SqrtE, {(P.DIVb){1'b0}}};
assign initU ={(P.DIVb+1){1'b0}};
assign initUM = {{1'b1}, {(P.DIVb){1'b0}}};
mux2 #(P.DIVb+1) Umux(UNext[P.DIVCOPIES-1], initU, IFDivStartE, UMux);
mux2 #(P.DIVb+1) UMmux(UMNext[P.DIVCOPIES-1], initUM, IFDivStartE, UMMux);
flopen #(P.DIVb+1) UReg(clk, FDivBusyE, UMux, U[0]);
@ -85,7 +85,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
if(P.RADIX == 4) begin
mux2 #(2) cuppermux4(2'b00, 2'b00, SqrtE, initCUpper); // *** Remove this soon
end else begin
mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper);
mux2 #(2) cuppermux2(2'b10, 2'b10, SqrtE, initCUpper);
end
assign initC = {initCUpper, {P.DIVb{1'b0}}};
@ -110,7 +110,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
end else begin: stage
logic j1,j0;
assign j0 = (i == 0 & ~C[0][P.DIVb+1]);
assign j1 = (i == 1 & ~C[0][P.DIVb+1]);
assign j1 = (i == 1 & ~C[0][P.DIVb+1]) || (i == 0 & (C[0][P.DIVb-1] ^ C[0][P.DIVb]));
fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .j0,
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));