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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Pulled brev8 out of byteop so redundant byteop logic is not needed in zbkb
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@ -103,7 +103,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
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// ZBKB Unit
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if (P.ZBKB_SUPPORTED) begin: zbkb
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zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
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zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
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end else assign ZBKBResult = '0;
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// ZBKX Unit
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@ -30,24 +30,22 @@
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module byteop #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, // Operands
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input logic [WIDTH-1:0] RevA, // Reversed A
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input logic [1:0] ByteSelect, // LSB of Immediate
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output logic [WIDTH-1:0] ByteResult); // rev8, orcb result
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logic [WIDTH-1:0] OrcBResult, Rev8Result, Brev8Result;
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logic [WIDTH-1:0] OrcBResult, Rev8Result;
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genvar i;
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for (i=0;i<WIDTH;i+=8) begin:loop
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assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
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assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
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assign Brev8Result[i+7:i] = RevA[WIDTH-1-i:WIDTH-i-8];
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end
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// ByteOp Result Mux
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// mux3 #(WIDTH) byteresultmux(Rev8Result, Brev8Result, OrcBResult, ByteSelect, ByteResult);
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always_comb begin
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if (ByteSelect[0] == 1'b0) ByteResult = Rev8Result;
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else if (ByteSelect[1] == 1'b0) ByteResult = OrcBResult;
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else ByteResult = Brev8Result;
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end
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else /*if (ByteSelect[1] == 1'b0) */ ByteResult = OrcBResult;
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end
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endmodule
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@ -45,7 +45,7 @@ module zbb #(parameter WIDTH=32) (
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mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
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cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
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byteop #(WIDTH) bu(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult);
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byteop #(WIDTH) bu(.A, .ByteSelect({B[10], B[0]}), .ByteResult);
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ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
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// ZBBSelect[2] differentiates between min(u) vs max(u) instruction
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@ -26,21 +26,26 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module zbkb #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, RevA,
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input logic [WIDTH-1:0] A, B,
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input logic W64,
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input logic [2:0] Funct3,
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input logic [2:0] ZBKBSelect,
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output logic [WIDTH-1:0] ZBKBResult
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);
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logic [WIDTH-1:0] ByteResult; // rev8, brev8
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logic [WIDTH-1:0] Brev8Result; // rev8, brev8
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logic [WIDTH-1:0] PackResult; // pack, packh, packw (RB64 only)
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logic [WIDTH-1:0] ZipResult; // zip, unzip
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// brev8 just uses wires
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genvar i, j;
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for (i=0;i<WIDTH/8;i=i+1)
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for (j=0; j<8; j=j+1)
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assign Brev8Result[i*8+j] = A[i*8+7-j];
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byteop #(WIDTH) rev(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult);
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packer #(WIDTH) pack(.A, .B, .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult);
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zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult);
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// ZBKB Result Select Mux
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mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);
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mux3 #(WIDTH) zbkbresultmux(Brev8Result, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);
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endmodule
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