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remove redundant mux

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This commit is contained in:
Kevin Kim 2024-03-03 13:00:20 -08:00
parent 2547e4c6d1
commit 0ff59ff157
1 changed files with 2 additions and 3 deletions
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src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -80,12 +80,11 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
flopen #(P.DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
// C register/initialization mux
// Initialize C to -1 for sqrt and -R for division
logic [1:0] initCUpper;
if(P.RADIX == 4) begin
mux2 #(2) cuppermux4(2'b00, 2'b00, SqrtE, initCUpper); // *** Remove this soon
assign initCUpper = 2'b00;
end else begin
mux2 #(2) cuppermux2(2'b10, 2'b10, SqrtE, initCUpper);
assign initCUpper = 2'b10;
end
assign initC = {initCUpper, {P.DIVb{1'b0}}};