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changed cycle count to account for integer bit generation for sqrt

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Kevin Kim 2024-03-03 10:29:32 -08:00
parent c45d67f8ba
commit 6c24afaf98
1 changed files with 1 additions and 1 deletions
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src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -71,7 +71,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
// The datapath produces rk bits per cycle, so Cycles = ceil (ResultBitsE / rk)
always_comb begin
if (SqrtE) FPResultBitsE = Nf + 2 + 0; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1
if (SqrtE) FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1
else FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits
if (P.IDIV_ON_FPU) ResultBitsE = IntDivE ? IntResultBitsE : FPResultBitsE;