Resolved merge conflicts

docs/docker/Makefile

@@ -3,16 +3,30 @@ CVW_GIT?=""
 
 commanline:
 	podman run -it --rm \
-    -v cvw_temp:/home/cad/cvw \
-    -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
-    --privileged --network=host \
-    wallysoc/regression_wally /bin/bash
+	-v cvw_temp:/home/cad/cvw \
+	-v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
+	--privileged --network=host \
+	wallysoc/regression_wally /bin/bash
 
 regression_openhw_cvw:
 	podman run \
 	-e CVW_GIT=$(CVW_GIT) \
-    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
-    -v cvw_temp:/home/cad/cvw \
-    -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
-    --privileged --network=host \
-    --rm wallysoc/regression_wally
+	-e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
+	-v cvw_temp:/home/cad/cvw \
+	-v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
+	--privileged --network=host \
+	--rm wallysoc/regression_wally
+
+push_hub:
+	podman push wallysoc/ubuntu_wally:latest
+	podman push wallysoc/toolchains_wally:latest
+	podman push wallysoc/regression_wally:latest
+
+update_ubuntu:
+	podman build -t wallysoc/ubuntu_wally -f Dockerfile.ubuntu .
+
+update_toolchains:
+	podman build -t wallysoc/toolchains_wally -f Dockerfile.builds .
+
+update_regression:
+	podman build -t wallysoc/regression_wally -f Dockerfile.regression .

fpga/generator/Makefile

@@ -57,7 +57,8 @@ PreProcessFiles:
 	# modify config  *** RT: eventually setup for variably defined sized memory
 	#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
 	# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
-	sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
+	sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
+	sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
 
 $(dst)/%.log: %.tcl
 	mkdir -p IP

fpga/generator/insert_debug_comment.sh

@@ -4,7 +4,7 @@
 ##
 ## Written: Rose Thompson ross1728@gmail.com
 ## Created: 20 January 2023
-## Modified: 16 April 2024
+## Modified: 22 April 2024
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
 ## https://github.com/openhwgroup/cvw
@@ -29,21 +29,12 @@
 # Then it processes them to add mark_debug on signals needed by the FPGA's ILA.
 copiedDir="../src/CopiedFiles_do_not_add_to_repo"
 while read line; do
-    # older versions of bash are incompatible with readarray -d :(
-    #readarray -d ":" -t StrArray <<< "$line"
-    #file="${copiedDir}/${StrArray[0]}"
-    #signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
-    fileName=`echo $line | cut -d  ":" -f 1`
-    file=${copiedDir}/$fileName
-    signal=`echo $line | cut -d  ":" -f 2`
-    echo $file
-    echo $signal
+    readarray -d ":" -t StrArray <<< "$line"
+    file="${copiedDir}/${StrArray[0]}"
+    signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
     readarray -d " " -t SigArray <<< $signal
-    sigType=`echo $signal | cut -d " " -f 1`
-    sigType=`echo $sigType | awk '{$1=$1};1'`
-    sigName=`echo $signal | cut -d " " -f 2`
-    sigName=`echo $sigName | awk '{$1=$1};1'`
-    #sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
-    #sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
-    find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" 
+    sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
+    sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1' | tr -d "\015"`
+    filepath=`find $copiedDir -wholename $file`
+    sed -i "s/\(.*${sigType}.*${sigName}.*\)/(\* mark_debug = \"true\" \*)\1/g" $filepath
 done < ../constraints/marked_debug.txt

sim/verilator/Makefile

@@ -9,6 +9,10 @@ SHELL := /bin/bash
 OPT=
 PARAMS?=-DVERILATOR=1 --no-trace-top
 NONPROF?=--stats
+VERILATOR_DIR=${WALLY}/sim/verilator
+SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+
+
 WALLYCONF?=rv64gc
 TEST?=arch64i
 
@@ -26,36 +30,37 @@ DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
 default: run
 
 profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
-	$(WORKING_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 
+	$(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 
 	mv gmon.out gmon_$(WALLYCONF).out
-	gprof $(WORKING_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log
+	gprof $(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log
 	verilator_profcfunc gmon_$(WALLYCONF).log > gmon_$(WALLYCONF).log2
-	mkdir -p $(WORKING_DIR)/logs_profiling
-	mv gmon_$(WALLYCONF)* $(WORKING_DIR)/logs_profiling
-	echo "Please check $(WORKING_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
+	mkdir -p $(VERILATOR_DIR)/logs_profiling
+	mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
+	echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
 
-run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF)
-	mkdir -p $(WORKING_DIR)/logs
-#	time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log
-	time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST)
-#	echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
+run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
+	mkdir -p $(VERILATOR_DIR)/logs
+#	wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST) 2>&1 > $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log
+	wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
+#	echo "Please check $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
 	
-obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
-	mkdir -p obj_dir_non_profiling
-	time verilator \
-	--Mdir obj_dir_non_profiling -o Vtestbench_$(WALLYCONF) \
-	-cc --binary \
+
+wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(SOURCE)
+	verilator \
+	--Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \
+	--binary \
 	$(OPT) $(PARAMS) $(NONPROF) \
 	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
-	$(INCLUDE_PATH) \
-	wrapper.c \
-	$(SOURCES)
+	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \
+	${WALLY}/sim/verilator/wrapper.c \
+	${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+
 	
 obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
 	mkdir -p obj_dir_profiling
-	time verilator \
+	verilator \
 	--Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \
-	-cc --binary \
+	--binary \
 	--prof-cfuncs $(OPT) $(PARAMS) \
 	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
 	$(INCLUDE_PATH) \
@@ -63,7 +68,7 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
 	$(SOURCES)
 
 questa:
-	time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)"
+	vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)"
 
 clean:
-	rm -rf $(WORKING_DIR)/obj_dir_non_profiling $(WORKING_DIR)/obj_dir_profiling $(WORKING_DIR)/logs $(WORKING_DIR)/logs_profiling
+	rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling

src/generic/mem/rom1p1r.sv

@@ -35,8 +35,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
 
 `ifdef VERILATOR
     import "DPI-C" function string getenvval(input string env_name);
-//    string       WALLY_DIR = getenvval("WALLY"); 
-    string       WALLY_DIR = "~/cvw";
+    string       WALLY_DIR = getenvval("WALLY"); 
 `else
     string       WALLY_DIR = "$WALLY";
 `endif