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https://github.com/openhwgroup/cvw
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Started parameterizing FMA
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@ -115,6 +115,9 @@ localparam CVTLEN = (ZFA_SUPPORTED & D_SUPPORTED) ? `max(BASECVTLEN, 32'd84) : B
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localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN));
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localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
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// size of FMA output
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localparam FMALEN = 3*NF + 6;
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// NORMSHIFTSIZE is the bits out of the normalization shifter
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// RV32F: max(32+23+1, 2(23)+4, 3(23)+6) = 3*23+6 = 75
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// RV64F: max(64+23+1, 64 + 23 + 2, 3*23+6) = 89
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@ -125,8 +128,8 @@ localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
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// because NORMSHIFTSZ becomes limited by convert rather than divider
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// The two extra bits are necessary because shiftcorrection dropped them for fcvt.
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// May be possible to remove these two bits by modifying shiftcorrection
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localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (3*NF+8));
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//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+8));
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localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (FMALEN + 2));
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//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));
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localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ)
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localparam CORRSHIFTSZ = NORMSHIFTSZ-2; // Drop leading 2 integer bits
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@ -193,6 +193,7 @@ localparam cvw_t P = '{
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CVTLEN : CVTLEN,
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LLEN : LLEN,
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LOGCVTLEN : LOGCVTLEN,
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FMALEN : FMALEN,
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NORMSHIFTSZ : NORMSHIFTSZ,
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LOGNORMSHIFTSZ : LOGNORMSHIFTSZ,
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CORRSHIFTSZ : CORRSHIFTSZ,
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@ -287,6 +287,7 @@ typedef struct packed {
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int LOGCVTLEN;
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int NORMSHIFTSZ;
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int LOGNORMSHIFTSZ;
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int FMALEN;
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int CORRSHIFTSZ;
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// division constants
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@ -34,13 +34,13 @@ module fma import cvw::*; #(parameter cvw_t P) (
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input logic XZero, YZero, ZZero, // is the input zero
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input logic [2:0] OpCtrl, // operation control
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output logic ASticky, // sticky bit that is calculated during alignment
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output logic [3*P.NF+5:0] Sm, // the positive sum's significand
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output logic [P.FMALEN-1:0] Sm, // the positive sum's significand
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output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
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output logic As, // the aligned addend's sign (modified Z sign for other operations)
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output logic Ps, // the product's sign
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output logic Ss, // the sum's sign
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output logic [P.NE+1:0] Se, // the sum's exponent
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output logic [$clog2(3*P.NF+7)-1:0] SCnt // normalization shift count
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output logic [$clog2(P.FMALEN+1)-1:0] SCnt // normalization shift count
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);
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// OpCtrl:
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@ -54,8 +54,8 @@ module fma import cvw::*; #(parameter cvw_t P) (
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// 111 - sub
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logic [2*P.NF+1:0] Pm; // the product's significand in U(2.2Nf) format
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logic [3*P.NF+5:0] Am; // addend aligned's mantissa for addition in U(NF+4.2NF)
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logic [3*P.NF+5:0] AmInv; // aligned addend's mantissa possibly inverted
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logic [P.FMALEN-1:0] Am; // addend aligned's mantissa for addition in U(NF+4.2NF)
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logic [P.FMALEN-1:0] AmInv; // aligned addend's mantissa possibly inverted
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logic [2*P.NF+1:0] PmKilled; // the product's mantissa possibly killed U(2.2Nf)
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logic KillProd; // set the product to zero before addition if the product is too small to matter
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logic [P.NE+1:0] Pe; // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
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@ -89,6 +89,6 @@ module fma import cvw::*; #(parameter cvw_t P) (
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fmaadd #(P) add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
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fmalza #(3*P.NF+6, P.NF) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
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fmalza #(P.FMALEN, P.NF) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
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endmodule
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