1567 Commits

Author	SHA1	Message	Date
David Harris	bd6eef2a51	Initial implementation of SVNAPOT and SVPBMT does not break regression	2023-08-25 18:33:08 -07:00
David Harris	c6631ef808	Added N and PBMT bits to MMU PTE	2023-08-24 19:44:46 -07:00
David Harris	0e16203cd8	Merge pull request #393 from ross144/main ... Implemented and tested CBOZ instruction	2023-08-24 19:17:38 -07:00
David Harris	c45fbe1ffe	Merge pull request #394 from harshinisrinath1001/main ... Improved testing of csri with priv.S!	2023-08-24 19:16:50 -07:00
harshinisrinath	c9112ff18d	Improved testing of csri with priv.S	2023-08-24 18:39:15 -07:00
Ross Thompson	99455ad851	Fixed minor performance bug with CBOZ.	2023-08-24 17:08:20 -05:00
Ross Thompson	914b6f9734	Now have CBOZ instructions working!	2023-08-24 16:47:35 -05:00
David Harris	f5dab9f2fe	Check for legal SATP mode values	2023-08-24 05:18:04 -07:00
Ross Thompson	00e65c4ae7	Oups there was a bug in the SATP fix. RV32GC was broken by the changes.	2023-08-23 09:42:46 -05:00
Ross Thompson	45a7dfba28	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-08-23 09:15:13 -05:00
Jacob Pease	140d246fb5	Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP.	2023-08-22 16:25:56 -05:00
Ross Thompson	c2a9fbb1fc	Fixed bug with the cbo.inval clearing already cleared lines.	2023-08-21 17:51:51 -05:00
Ross Thompson	05d590b0b9	Fixed issue when with flush miss.	2023-08-18 16:36:13 -05:00
Ross Thompson	fc3fccafe9	Now we have invalidate, clean, and flush working.	2023-08-18 16:32:22 -05:00
Ross Thompson	4eeba9bed9	Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.	2023-08-18 15:59:39 -05:00
Ross Thompson	5c408454b8	Might have working cbo clean and flush instructions.	2023-08-18 14:48:21 -05:00
Ross Thompson	21129dde71	Fixed cbo instruction decode.	2023-08-18 11:32:30 -05:00
Ross Thompson	9dcc70d6c1	Updated the hazard logic for CMO operations.	2023-08-17 17:58:49 -05:00
Ross Thompson	072126b967	Found first bug in CMO implementation.	2023-08-17 16:57:54 -05:00
Ross Thompson	f9df1fda23	CMOZ now implemented in the D cache.	2023-08-17 12:46:40 -05:00
Ross Thompson	624b3e3ab2	Added clean and flush to cache fsm.	2023-08-16 14:23:56 -05:00
Ross Thompson	5281077531	More progress towards cmo.	2023-08-15 18:17:15 -05:00
Ross Thompson	9f37fef145	The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.	2023-08-14 16:39:18 -05:00
Ross Thompson	0eac74ac7b	Initial CMO implementation. Just adds control signals into the L1 caches.	2023-08-14 15:43:12 -05:00
Ross Thompson	7a196d3fa7	Cache cleanup.	2023-07-31 14:12:53 -05:00
Ross Thompson	faaf43fa10	Merge pull request #372 from davidharrishmc/dev ... PLIC part select warnings fixed	2023-07-31 11:28:28 -04:00
David Harris	6ff2b0cc2c	Merge pull request #373 from harshinisrinath1001/main ... Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing	2023-07-30 22:46:44 -07:00
Harshini Srinath	7ed4cf97ed	Fixed formatting	2023-07-30 18:36:25 -07:00
Harshini Srinath	603ed2160e	Fixed formatting	2023-07-30 18:30:23 -07:00
Harshini Srinath	acbbe7941a	Fixed formatting	2023-07-30 18:27:22 -07:00
Harshini Srinath	e4de9ae87c	Fixed formatting	2023-07-30 18:18:24 -07:00
Harshini Srinath	4c1a07eb9c	Fixed formatting	2023-07-30 18:06:25 -07:00
Harshini Srinath	1badc8a8c5	Fixed formatting	2023-07-30 18:00:39 -07:00
Harshini Srinath	41555b149e	Fixed formatting	2023-07-30 17:54:47 -07:00
Harshini Srinath	8e97224cd7	Fixed formatting	2023-07-30 17:46:23 -07:00
Harshini Srinath	469b03577d	Fixed formatting	2023-07-30 17:39:37 -07:00
Harshini Srinath	141384f60f	Fixed formatting	2023-07-30 17:38:22 -07:00
Harshini Srinath	bbbd5f6b2d	Fixed spacing	2023-07-30 17:32:46 -07:00
Harshini Srinath	d7b2d84124	Fixed spacing	2023-07-30 17:22:40 -07:00
Harshini Srinath	b129068a92	Fixed spacing	2023-07-30 17:21:52 -07:00
Harshini Srinath	49823ccd45	Fixed spacing	2023-07-30 17:21:22 -07:00
Harshini Srinath	36108e4b52	Fixed spacing	2023-07-30 17:18:25 -07:00
Harshini Srinath	d88b2fd9c1	Fixed spacing	2023-07-30 16:59:27 -07:00
Harshini Srinath	d69d0ececc	Fixed spacing	2023-07-30 16:57:57 -07:00
David Harris	d58ece3d44	renamed test-shared.vh to config-shared.vh	2023-07-30 05:22:39 -07:00
David Harris	28823aca6e	Cleaned up lint for plic_apb part select	2023-07-30 02:00:38 -07:00
David Harris	654cafb7f7	Fixed Questa warnings in plic_apb about part select out of bounds	2023-07-30 01:54:41 -07:00
Ross Thompson	7e06775135	Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.	2023-07-28 11:20:29 -05:00
Ross Thompson	15dc76310e	Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN.	2023-07-26 15:08:01 -05:00
Ross Thompson	2dac02c14c	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-07-25 15:13:07 -05:00
David Harris	ca62487e4c	Formatting cleanup	2023-07-25 05:11:38 -07:00
Ross Thompson	b1f7a5768f	Removed all old references to the old flash card controller. ... Added git submodule for the flash card in addins. Replicated flash card top level for our changes into the fpga/src directory.	2023-07-24 15:45:57 -05:00
Ross Thompson	63afd95ad3	Fixed bugs in boot and new flash card merge. Works with arty a7 now.	2023-07-22 15:52:25 -05:00
Ross Thompson	a89a1e675c	Merge branch 'boot' into mergeBoot ... Merges Jacob's new sdc controller into wally.	2023-07-21 17:43:45 -05:00
Ross Thompson	f895898d22	Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.	2023-07-21 16:31:26 -05:00
Ross Thompson	d04d2afed2	Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.	2023-07-21 13:06:27 -05:00
Jacob Pease	380d96b359	Working new boot process. Buildroot package for sdc.	2023-07-20 14:15:59 -05:00
Ross Thompson	c0966c32e5	Improved critical path.	2023-07-19 14:59:37 -05:00
Ross Thompson	538efaf771	Optimized critial path in ifu's spill logic.	2023-07-19 14:13:46 -05:00
Ross Thompson	af0e33209f	Removed QEMU from configurations.	2023-07-19 10:23:55 -05:00
Ross Thompson	b756b248b4	Wow. The newest version of Vivado does not like the enums as parameters. ... The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.	2023-07-18 15:07:10 -05:00
Ross Thompson	42e6364b3d	Merge branch 'main' of github.com:ross144/cvw	2023-07-17 15:52:27 -05:00
Ross Thompson	c82638774f	Updated the FPGA zero stage bootloader.	2023-07-17 15:52:13 -05:00
Ross Thompson	50bc679fef	Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.	2023-07-14 16:31:44 -05:00
Jacob Pease	b3aaa87cba	Modified bootloader to access GUID partitions. SDC interrupt to PLIC. ... Since writing an SD card image generation script, the bootloader needed to be altered to access individual binaries from specific partitions. A new file, gpt.c with it's header gpt.h, have been added to the bootloader to facilitate this. The SDC has been added to the device tree for the VCU108 board. Additionally the SDC interrupt signal was added to the PLIC node in the device tree. The PLIC itself was modified to accept the SDC interrupt signal.	2023-07-14 13:36:44 -05:00
David Harris	644afa16cd	Clean up privilege rs1 decoding and implement svinval as sfence.vma	2023-07-13 02:41:17 -07:00
Ross Thompson	625192d9a4	Merge branch 'main' of github.com:ross144/cvw into main	2023-07-11 15:08:26 -05:00
Ross Thompson	38f32805ae	Created separate temporary testbench for xcelium.	2023-07-11 15:07:33 -05:00
Ross Thompson	4c4eb080ee	RTL changes for Xcelium.	2023-07-11 10:51:02 -05:00
Ross Thompson	12beada55b	Fixed the privilege decoder bug which prevented the fpga linux boot.	2023-07-10 17:00:06 -05:00
Ross Thompson	beaec570c7	Merge pull request #359 from davidharrishmc/dev ... CSR updates	2023-07-10 13:16:57 -04:00
David Harris	e713ba8d3e	MENVCFG only exists if U_SUPPORTED	2023-07-09 18:25:07 -07:00
Ross Thompson	27f6f00402	Changes for xcelium.	2023-07-07 18:22:28 -05:00
Ross Thompson	cdf73d3b51	Updated comments.	2023-07-06 15:24:26 -05:00
Ross Thompson	e4555dc4af	Removed unused parameter.	2023-07-06 14:57:07 -05:00
Ross Thompson	2ce8b66574	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-07-06 14:55:43 -05:00
David Harris	369e8fb5ec	Removed outdated commment about endianness	2023-07-06 12:41:46 -07:00
David Harris	869a7cb827	Removed MTINST, which is not used in a system without a hypervisor	2023-07-06 12:40:53 -07:00
Ross Thompson	a963e50e88	It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga.	2023-07-06 14:07:37 -05:00
Ross Thompson	df56ff73c0	This is at least functionally correct, but has verilator lint issues.	2023-07-06 11:53:34 -05:00
Ross Thompson	c000366d3e	closer, but the wally32/64priv tests are failing.	2023-07-05 17:47:38 -05:00
Ross Thompson	98147e116a	Partially solved fpga boot.	2023-07-05 17:30:55 -05:00
David Harris	269bb688ea	Fixed comment typo	2023-07-04 11:34:58 -07:00
David Harris	410ef01627	fixed spacing in fdivsqrt	2023-07-04 11:27:36 -07:00
David Harris	afe66d0ee4	Added prefetch instructions; sent cbo instructions to LSU	2023-07-02 10:55:35 -07:00
David Harris	723b8266cb	Added prefetch signals	2023-07-02 10:06:58 -07:00
David Harris	482e4e6e92	Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions	2023-07-02 09:35:05 -07:00
David Harris	c48283801a	Fixed csr typos	2023-07-02 02:01:40 -07:00
David Harris	61208e486c	Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode	2023-07-02 02:00:27 -07:00
David Harris	b6ae5661b4	Added environment configuration control (menvcfg/senvcfg) of cbo instructions	2023-07-02 01:52:25 -07:00
David Harris	15314a9c9a	Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations	2023-07-02 00:34:30 -07:00
David Harris	41e9f20943	improved decoder checking atomic and RW and MW and privileged instructions	2023-07-02 00:02:03 -07:00
David Harris	e34ef4d636	improved decoder checking atomic instructions	2023-07-01 23:10:57 -07:00
David Harris	d930be332e	Improved instruction decoding for illegal floating-point loads/stores and fences	2023-07-01 22:48:04 -07:00
Ross Thompson	f5cee3fb66	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-18 16:37:19 -05:00
David Harris	c383407d5c	Removed redundant and not-covered atomic check from StoreStallD	2023-06-16 16:05:53 -07:00
Ross Thompson	c44d4321fb	FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.	2023-06-16 15:40:13 -05:00
Ross Thompson	bdc5656ef3	Added comment to uart LCR to check reset value after updating FPGA.	2023-06-15 15:39:51 -05:00
Ross Thompson	4428babda9	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
Ross Thompson	85567841eb	Merge branch 'testbench-params2'	2023-06-15 15:31:13 -05:00
Ross Thompson	d2219023c3	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 14:57:23 -05:00
David Harris	3ca271b6a7	Added input gating on FPU	2023-06-15 12:38:33 -07:00
David Harris	9e839988dc	Gated MDU to save power; doesn't seem to have affected simulation time	2023-06-15 12:17:23 -07:00
David Harris	9f88848832	Bit manipulation comment cleanup	2023-06-15 12:16:46 -07:00
Ross Thompson	75b5c23edd	Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.	2023-06-15 14:05:44 -05:00
David Harris	a62211bad1	Gated inputs to BMU when inactive to save power and simulation time	2023-06-15 11:56:59 -07:00
Ross Thompson	009d8966e9	Got the srams parameterized correctly now.	2023-06-15 13:42:24 -05:00
David Harris	d3aebc00d4	Fixed UART merge conflict	2023-06-15 11:36:37 -07:00
Ross Thompson	b8a243827b	Found a whole bunch of files still using the old `define configurations.	2023-06-15 13:09:07 -05:00
Harshini Srinath	dd7c13cc2d	Update wallypipelinedsoc.sv ... Program clean up	2023-06-15 10:39:37 -07:00
Harshini Srinath	b4469fd3bf	Update wallypipelinedcore.sv ... Program clean up	2023-06-15 10:38:38 -07:00
Harshini Srinath	85a513e542	Update cvw.sv ... Program clean up	2023-06-15 10:29:33 -07:00
Harshini Srinath	b5354a811e	Update uncore.sv ... Program clean up	2023-06-15 10:23:47 -07:00
Harshini Srinath	85b982f569	Update uart_apb.sv ... Program clean up	2023-06-15 10:21:46 -07:00
Harshini Srinath	59178a2e56	Update uartPC16550D.sv ... Program clean up	2023-06-15 10:20:29 -07:00
Harshini Srinath	d02891d244	Update rom_ahb.sv ... Program clean up	2023-06-15 10:13:15 -07:00
Harshini Srinath	e227f71d46	Update ram_ahb.sv ... Program clean up	2023-06-15 10:10:38 -07:00
Harshini Srinath	57f4c8a3e4	Update plic_apb.sv ... Program clean up	2023-06-15 10:08:16 -07:00
Harshini Srinath	cf25e9ce49	Update gpio_apb.sv ... Program clean up	2023-06-15 10:04:28 -07:00
Harshini Srinath	a8fa38ff14	Update clint_apb.sv ... Program clean up	2023-06-15 09:59:11 -07:00
David Harris	325a670435	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-06-15 07:01:44 -07:00
Ross Thompson	60e87b08c4	Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s.	2023-06-14 15:28:58 -05:00
Harshini Srinath	3593762cfa	Merge branch 'main' into main	2023-06-14 11:52:45 -07:00
David Harris	430537a052	Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this.	2023-06-14 09:44:52 -07:00
David Harris	9da4005a1e	Removed *** from UART code	2023-06-14 08:47:01 -07:00
David Harris	5a2bcb917f	Removed QEMU from UART	2023-06-14 08:39:01 -07:00
Harshini Srinath	3f8cd8932c	Update csrs.sv ... Program clean up	2023-06-13 22:16:43 -07:00
Harshini Srinath	12af05da02	Update csrm.sv ... Program clean up	2023-06-13 22:08:06 -07:00
Harshini Srinath	a213f7d5a4	Update csrc.sv ... Program clean up	2023-06-13 21:54:47 -07:00
Harshini Srinath	6aba0187d7	Update csr.sv ... Program clean up	2023-06-13 21:12:49 -07:00
harshini	8570b2f332	deleting CodeAligner file	2023-06-13 17:41:37 -07:00
Harshini Srinath	9e1f03f93b	Update ahbapbbridge.sv ... Program clean up	2023-06-12 20:49:46 -07:00
Harshini Srinath	2c6322647f	Update trap.sv ... Program clean up	2023-06-12 20:31:44 -07:00
Harshini Srinath	dba1a77e5f	Update privmode.sv ... Program clean up	2023-06-12 20:27:48 -07:00
Harshini Srinath	63a7649179	Update privileged.sv ... Program clean up	2023-06-12 20:26:07 -07:00
Harshini Srinath	d2a41a6422	Update csru.sv ... Program clean up	2023-06-12 20:21:55 -07:00
Harshini Srinath	6866a9c541	Update csrsr.sv ... Program clean up	2023-06-12 20:19:47 -07:00
Harshini Srinath	fbdf76629f	Update csrsr.sv ... Program clean up	2023-06-12 20:15:29 -07:00
Harshini Srinath	120cde2aea	Update csrs.sv ... Program clean up	2023-06-12 19:53:41 -07:00
Harshini Srinath	6305412d57	Update csrm.sv ... Program clean up	2023-06-12 19:42:45 -07:00
Harshini Srinath	61d50a18da	Update csri.sv ... Program clean up	2023-06-12 19:32:04 -07:00
Harshini Srinath	02a11278fc	Update csrc.sv ... Program clean up	2023-06-12 19:03:34 -07:00
Harshini Srinath	a2645dd576	Update csr.sv ... Program clean up	2023-06-12 18:51:37 -07:00
Harshini Srinath	a1a9d668c5	Update pmpchecker.sv ... Program clean up	2023-06-12 18:44:36 -07:00
Harshini Srinath	09ac5b1817	Update pmpadrdec.sv ... Program clean up	2023-06-12 18:41:47 -07:00
Harshini Srinath	ccb81c84f4	Update pmachecker.sv ... Program clean up	2023-06-12 18:39:36 -07:00
Harshini Srinath	5a6a932b7e	Update mmu.sv ... Program clean up	2023-06-12 18:36:04 -07:00
Harshini Srinath	a57a619349	Update hptw.sv ... Program clean up	2023-06-12 18:31:38 -07:00
Harshini Srinath	ec0454111f	Update adrdecs.sv ... Program clean up	2023-06-12 18:22:32 -07:00
Harshini Srinath	b1ee6bfde5	Update adrdec.sv ... Program clean up	2023-06-12 17:28:21 -07:00
Harshini Srinath	7c51dd18dd	Update mul.sv	2023-06-12 14:00:37 -07:00
Harshini Srinath	08459c4cc4	Update mdu.sv ... Program clean up	2023-06-12 13:54:54 -07:00
Harshini Srinath	bdd2206817	Update div.sv ... Program clean up	2023-06-12 13:47:09 -07:00
Harshini Srinath	15928c5d7b	Update swbytemask.sv ... Program clean up	2023-06-12 13:37:35 -07:00
Harshini Srinath	f3a7d9030c	Update subwordwrite.sv ... Program clean up	2023-06-12 13:35:27 -07:00
Harshini Srinath	f1f21f0896	Update subwordread.sv ... Program clean up	2023-06-12 13:31:54 -07:00
Harshini Srinath	4d0be994aa	Update lsu.sv ... Program clean up	2023-06-12 13:29:18 -07:00
Harshini Srinath	a45f2fd044	Update lrsc.sv ... Program clean up	2023-06-12 13:14:36 -07:00
Harshini Srinath	d21fd3da44	Update dtim.sv ... Program clean up	2023-06-12 13:11:24 -07:00
Harshini Srinath	048e100805	Update atomic.sv ... Program clean up	2023-06-12 13:08:54 -07:00
Harshini Srinath	ec1aa29edc	Update amoalu.sv ... Program clean up	2023-06-12 12:54:50 -07:00
Harshini Srinath	9d0fc0a138	Update spill.sv ... Program clean up	2023-06-12 12:50:11 -07:00
Harshini Srinath	19e8acff70	Update irom.sv ... Program clean up	2023-06-12 12:44:09 -07:00
Harshini Srinath	a5561c2cf6	Update ifu.sv ... Program clean up	2023-06-12 12:38:52 -07:00
Harshini Srinath	b5c655b1c3	Update decompress.sv ... Program clean up	2023-06-12 12:27:55 -07:00
Harshini Srinath	d0ede93dc1	Update CodeAligner.py ... Program clean up	2023-06-12 12:25:47 -07:00
Harshini Srinath	5f73c9727f	Update shifter.sv ... Program clean up	2023-06-12 12:23:45 -07:00
Harshini Srinath	0f36cbd830	Update regfile.sv ... Program clean up	2023-06-12 12:21:25 -07:00
Harshini Srinath	f1cef043c6	Update ieu.sv ... Program clean up	2023-06-12 12:19:04 -07:00
Harshini Srinath	304adcb9b0	Update extend.sv ... Program clean up	2023-06-12 12:15:33 -07:00
Harshini Srinath	1d24a9c912	Update datapath.sv ... Program clean up	2023-06-12 12:13:58 -07:00
Ross Thompson	ee4352975c	This parameterizes the testbench but does not use the verilator updates or the new testbench.	2023-06-12 11:00:30 -05:00
Ross Thompson	7031a7b1ea	Merge pull request #327 from harshinisrinath1001/main ... Fixed the spacing in the fpu module	2023-06-12 11:53:52 -04:00
Harshini Srinath	0c324bce7b	Update prioritythermometer.sv ... Program clean up	2023-06-11 19:18:21 -07:00
Harshini Srinath	66856f31ca	Update or_rows.sv ... Program clean up	2023-06-11 19:16:37 -07:00
Harshini Srinath	250ea7668e	Update neg.sv ... Program clean up	2023-06-11 19:15:28 -07:00
Harshini Srinath	5a40272fd7	Update counter.sv ... Program clean up	2023-06-11 19:12:57 -07:00
Harshini Srinath	16028a5766	Update adder.sv ... Program clean up	2023-06-11 19:09:18 -07:00
Harshini Srinath	61b85d1c7f	Update unpackinput.sv ... Program clean up	2023-06-11 17:09:11 -07:00
Harshini Srinath	37ad074c4d	Update fctrl.sv ... Program clean up	2023-06-11 17:03:29 -07:00
Harshini Srinath	ac17b93a84	Update fcmp.sv ... Program clean up	2023-06-11 16:54:52 -07:00
Harshini Srinath	c19ba6c3f4	Update fsgninj.sv ... Program clean up	2023-06-11 16:52:00 -07:00
Harshini Srinath	cf39819bac	Update fregfile.sv ... Program clean up	2023-06-11 16:49:20 -07:00
Harshini Srinath	a98096aa7d	Update fpu.sv ... Program clean up	2023-06-11 16:43:31 -07:00
Harshini Srinath	4c4e6ca520	Update fhazard.sv ... Program clean up	2023-06-11 16:06:44 -07:00
Harshini Srinath	610ac81a71	Update fcvt.sv ... Program clean up	2023-06-11 16:05:14 -07:00
Harshini Srinath	e469e4fd20	Update fcvt.sv ... Program clean up	2023-06-11 15:59:20 -07:00
Ross Thompson	e27dfb8ce0	Merge branch 'verilator'	2023-06-11 15:28:04 -05:00
David Harris	29b48334d8	Fixed lint errors, presumably detected by latest version of verilator	2023-06-11 06:48:42 -07:00
David Harris	99fe09fb40	Merge pull request #322 from harshinisrinath1001/main ... Fixing spacing for ebu	2023-06-11 06:00:35 -07:00
Harshini Srinath	aead7cbe49	Update fctrl.sv ... Program clean up	2023-06-10 19:38:50 -07:00
Harshini Srinath	04a744c249	Update fcmp.sv ... Program clean up	2023-06-10 19:35:58 -07:00
Harshini Srinath	ffada57ea2	Update fcmp.sv ... Program clean up	2023-06-10 19:34:58 -07:00
Harshini Srinath	ec188987b8	Update fclassify.sv ... Program clean up	2023-06-10 19:30:18 -07:00
Harshini Srinath	9dc72c9e54	Update controllerinput.sv ... Program clean up	2023-06-10 18:26:06 -07:00
Harshini Srinath	dbdb3c69d3	Update ahbinterface.sv ... Program clean up	2023-06-10 18:18:16 -07:00
Harshini Srinath	dc0b95c4ac	Program clean up	2023-06-10 18:13:40 -07:00
Ross Thompson	c7536663c0	Merge pull request #319 from davidharrishmc/dev ... Renamed Performance Counter extension	2023-06-09 21:21:45 -04:00
David Harris	b70b0c7c5e	Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare	2023-06-09 14:40:01 -07:00
David Harris	df96900aa1	Added named support for Zicntr and Zihpm	2023-06-09 09:35:51 -07:00
Harshini Srinath	aafa5d6ec3	Update ebu.sv ... Code clean up	2023-06-09 08:53:27 -07:00
Harshini Srinath	570a628198	Update subcachelineread.sv ... Code clean up	2023-06-09 08:50:51 -07:00
Harshini Srinath	c49232f0d2	Update cacheway.sv ... Code clean up	2023-06-09 08:48:11 -07:00
Harshini Srinath	e7fb7403ef	Update cacheLRU.sv ... Code clean up	2023-06-09 08:43:38 -07:00
Harshini Srinath	19c1a0f99b	Update cache.sv ... Formatting clean up	2023-06-09 08:39:57 -07:00
Ross Thompson	a8a8422557	Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.	2023-06-09 09:28:24 -05:00
David Harris	75dc86ddc0	Merge pull request #313 from ross144/main ... Fix extraneous force in testbench which keep btb in reset.	2023-06-06 08:41:34 -07:00
David Harris	c9ca5108b1	Merge pull request #312 from ross144/main ... Fixed typo in coremark makefile.	2023-06-06 05:44:22 -07:00
Ross Thompson	918464c236	Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.	2023-06-05 15:42:05 -05:00
James Stine	3bd5bbce48	Update some spacing to make it look better	2023-06-05 11:03:06 -05:00
Ross Thompson	1ceea51d8b	Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.	2023-05-31 16:51:00 -05:00
Ross Thompson	a963f0af3a	Updated source code to be compatible with verilator 5.011 for lint only.	2023-05-31 10:44:23 -05:00
Ross Thompson	169539f773	Cleanup parameterization for verilator 5.010.	2023-05-31 10:02:34 -05:00
Ross Thompson	8e1476cb8c	Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt. ... This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state. Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk. The new implementation adds a FAULT state. When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE. There may still be a remaining bug here if the pipeline is stalled for another reason. However I don't think it is possible by construction. The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.	2023-05-30 15:20:24 -05:00
Ross Thompson	04d0fd94f0	Merge branch 'param-lim-merge'	2023-05-26 16:25:35 -05:00
Ross Thompson	3cc85349b5	Uncore is now parameterized.	2023-05-26 16:24:12 -05:00
Ross Thompson	1315a0bf4a	Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.	2023-05-26 16:00:14 -05:00
Jacob Pease	40f81d5da6	The Vivado-RISC-V SDC works. Wally is now booting through it.	2023-05-26 15:42:33 -05:00
Ross Thompson	f1b8689955	Finished fpu parameterization using Lim's method.	2023-05-26 14:40:06 -05:00
Ross Thompson	29e0357f21	fdiv is now parameterized using Lim's method.	2023-05-26 14:25:14 -05:00
Ross Thompson	81491e85e5	Parameterized fpu's unpack and fma using Lim's method.	2023-05-26 14:12:25 -05:00
Ross Thompson	c7e515634d	I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.	2023-05-26 13:56:51 -05:00
Ross Thompson	b517a96261	Update top level parameterized. Simulation slowed down to 4.5 minutes.	2023-05-26 12:13:11 -05:00
Ross Thompson	8cf38b28aa	The privileged unit is parameterized using Lim's method.	2023-05-26 12:03:46 -05:00
Ross Thompson	4d961bd080	Completed LSU parameterization based on Lim's changes.	2023-05-26 11:26:09 -05:00
Ross Thompson	d37e010aa4	Subwordread now parameterized.	2023-05-26 11:22:44 -05:00
Ross Thompson	02a788a083	PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.	2023-05-26 11:06:48 -05:00
Ross Thompson	0e1131d190	Progress on LSU.	2023-05-26 10:47:09 -05:00
Ross Thompson	0020d94b39	Updated mmu's tlb and hptw to use Lim's parameterization.	2023-05-24 18:02:22 -05:00
Ross Thompson	70c8828ac2	PM(P/A) checkers parameterized based on Lim's work.	2023-05-24 17:20:55 -05:00
Ross Thompson	fcb1c63f5f	Partial parameterization into mmu.	2023-05-24 16:12:41 -05:00
Ross Thompson	5f5f33787d	MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.	2023-05-24 15:01:35 -05:00
Ross Thompson	1299319d0b	More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.	2023-05-24 14:56:02 -05:00
Ross Thompson	052bc95966	More parameterization. Copied Lim. Still no slow down.	2023-05-24 14:49:22 -05:00
Ross Thompson	b91b54589e	Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.	2023-05-24 14:05:44 -05:00
Ross Thompson	6d2e3070a5	Merged changes.	2023-05-24 13:15:52 -05:00
Ross Thompson	80aa0888f3	Updated headers to local branch history predictors.	2023-05-24 12:52:42 -05:00
Ross Thompson	930fb67308	Trying to figure out why the parameterization slowed down modelsim so much.	2023-05-24 12:44:42 -05:00
Ross Thompson	69a9bf7055	Adds local history predictor. ... Fixes performance counters, but not coremark.	2023-05-23 18:53:46 -05:00
Ross Thompson	664231c0da	Merge branch 'localhistory' ... Repair to wave file. Created implementations of local history. Part of my Ph.D. research.	2023-05-22 10:13:31 -05:00
Ross Thompson	625d365f3e	Fixes load and store stall counters.	2023-05-22 10:08:49 -05:00
Ross Thompson	8f305bf3cf	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-05-11 14:56:53 -05:00
Ross Thompson	d545a2ec74	Partially working local history repair.	2023-05-11 14:56:26 -05:00
Ross Thompson	3a98fb8680	Baseline localhistory with speculative repair built.	2023-05-05 15:23:45 -05:00
Ross Thompson	42517bae6f	Fixed bug in local history predictor.	2023-05-04 16:54:41 -05:00
Ross Thompson	ee1e380fad	Almost working ahead pipelined local history predictor.	2023-05-04 16:17:31 -05:00
Ross Thompson	8235042ba2	Maybe I finally have the ahead pipelined local history predictor working.	2023-05-04 14:11:34 -05:00
Ross Thompson	060d40853a	Ahead pipelining is not yet working. :(	2023-05-03 17:41:38 -05:00
Ross Thompson	8b0791b6b5	I think ahead pipelining is working for local history.	2023-05-03 12:52:32 -05:00
Ross Thompson	414c79b923	Updated configs for local branch history `defines.	2023-05-02 11:11:04 -05:00
Ross Thompson	08b237b878	Added comment explaining the difference between global history and local history basic implementations.	2023-05-02 11:01:46 -05:00
Ross Thompson	0904a9b97f	Swapped the m and k parameters for local history predictor.	2023-05-02 10:52:41 -05:00
Ross Thompson	4eff75449a	Maybe have the baseline local history predictor working.	2023-05-01 15:45:27 -05:00
Ross Thompson	7437cb67e5	Merge branch 'main' into localhistory	2023-05-01 10:35:50 -05:00
David Harris	d5b718be38	IMMU exclude non word-sized accesses	2023-05-01 08:14:19 -07:00
Ross Thompson	67539a4af1	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-04-30 23:30:13 -05:00
David Harris	90b2a4882f	Fixed redundant check of SupportedFmt on fmv that caused coverage problem on fctrl	2023-04-29 05:58:40 -07:00
David Harris	6253c042b2	Merged coverage exclusions for PMP	2023-04-28 08:04:25 -07:00
David Harris	194b848fbf	PMA Checker coverage	2023-04-28 07:53:59 -07:00
David Harris	af7959a3e2	Commenting	2023-04-28 07:52:08 -07:00
David Harris	9843223ddd	Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues	2023-04-28 07:03:46 -07:00
Ross Thompson	d44251098f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-04-27 16:38:36 -05:00
David Harris	ca61cff33f	CSR code cleanup	2023-04-27 14:12:57 -07:00
David Harris	a929656d9a	Renamed byteUnit to byteop	2023-04-27 14:10:46 -07:00
Ross Thompson	7c0eb16e62	Fixed bug in cacheLRU when NUMWAYS = 2.	2023-04-27 14:30:01 -05:00
Liam	4d8eafd27d	Pmpadrdecs test cases changing AdrMode to 2 or 3 ... Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3 Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv	2023-04-27 12:23:35 -07:00
David Harris	6a5895e09f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-04-27 07:30:07 -07:00
Alexa Wright	09095422d0	Merge branch 'openhwgroup:main' into main	2023-04-26 16:26:30 -07:00
Alexa Wright	6ee8a9c0bd	Added better comment for the exclusion in privdec.sv	2023-04-26 16:25:55 -07:00
David Harris	0eb8dd7935	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-04-26 15:40:11 -07:00
David Harris	ea3e3a1469	Merge pull request #283 from SydRiley/main ... Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions	2023-04-26 15:40:01 -07:00
Sydeny	5bcd57dab9	Addressing Redundant logic around BadNanBox, fpu coverage from 96.61% to 96.77%	2023-04-26 14:35:43 -07:00
David Harris	7cc26861cd	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-04-26 05:53:42 -07:00
Alec Vercruysse	5612f30029	Cacheway Exclude FlushStage=1 when SetValidWay=1 ... We determined that this case is not hit even for i$, so this case is also excluded separately for i$. It could be a better idea to remove the ~FlushStage check completely (if we're sure). My reasoning for this one is written as a comment in the exclusion script: since a pipeline stall is asserted by the cache in the fetch stage (which happens before going into the WRITE_LINE state and asserting SetValidWay), there seems to be no way to trigger a FlushStage (FlushW for D$) while the stallM is active.	2023-04-25 20:30:46 -07:00
Alexa Wright	59d913949f	Excluded and added coverage for WFI test case.	2023-04-25 17:06:57 -07:00
Alec Vercruysse	857956ac1e	Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign ... FlushWay is always 1 for one way, but by default it is only 1 for way 0. The logic that advances FlushWay to ways 1, 2, and 3 only does so on a subset of conditions that SelFlush is high (in cachefsm), so this is unreachable for cachways 1-3.	2023-04-25 17:02:53 -07:00
David Harris	a5087818ba	Commented about Sstvecd trap vector alignment	2023-04-24 12:20:33 -07:00
David Harris	ee6a3f49f0	Added M suffix in atomic	2023-04-24 12:19:56 -07:00
Ross Thompson	5777b90407	Might actually have a correct implementation of local history branch prediction.	2023-04-24 13:05:28 -05:00
Ross Thompson	e81445be5d	Fixed the local branch predictor so that it at least compiles.	2023-04-24 11:06:53 -05:00
Diego Herrera Vicioso	d29dc30288	Excluded coverage for impossible cases in wficountreg and status.MPRV	2023-04-24 02:06:53 -07:00
David Harris	52f49ed24d	Fault on writes to odd-numbered PMPCFG in RV64	2023-04-22 15:32:39 -07:00
David Harris	3b299fb77a	Removed unproven fdivsqrt exclusion	2023-04-22 15:27:05 -07:00
David Harris	086556310c	Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.	2023-04-22 12:22:45 -07:00
David Harris	063e41806e	Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right	2023-04-22 10:07:48 -07:00
David Harris	8a59a4ce94	fdivsqrt cleanup	2023-04-20 17:35:01 -07:00
David Harris	86107e6136	continued cleanup	2023-04-20 16:48:23 -07:00
David Harris	33c0f64457	Reordered fdivsqrtpreproc to follow logic	2023-04-20 16:38:47 -07:00
David Harris	2c47268f50	Started fdivsqrtpreproc flow organization	2023-04-20 16:25:19 -07:00
David Harris	f2ae770e17	Fmv h/q comments in controller	2023-04-20 16:24:58 -07:00
David Harris	b9d641f13a	Merge pull request #256 from cturek/main ... Simplifying fds to follow diagram	2023-04-20 16:07:22 -07:00
David Harris	3a8d2db194	Merge pull request #262 from SydRiley/main ... removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%	2023-04-19 14:49:50 -07:00
Sydeny	a132ffa7f7	removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%	2023-04-19 13:30:12 -07:00
Alec Vercruysse	faaf266558	CacheFSM logic simplification for AMO operations ... Ran this by Ross.	2023-04-19 01:34:01 -07:00
Alec Vercruysse	de93bd6937	D$ scope-specific coverage exclusions (I$ logic that never fires) ... The InvalidateCache signal in the D$ is for I$ only, which causes some coverage issues that need exclusion. Another manual exclusion is due to the fact that D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush, so those transistions are excluded. There is some other small stuff to review (logic simplification, or an exclusion pragma if removing the redundent logic would make it harder to understand the code, as is the case in the FlushAdrCntEn assign statement, in my opinion).	2023-04-19 01:34:01 -07:00
Cedar Turek	49356aa4ca	created fdivsqrtcycles, moved cycles calculation from FSM to preproc	2023-04-18 16:14:45 -07:00
Cedar Turek	b1dd1a627f	gave integer bits to D instead of adding manually everywhere	2023-04-18 15:41:04 -07:00
Cedar Turek	914baf6bb1	moved D flop to preproc	2023-04-18 15:14:17 -07:00
Sydeny	ee5deb10a7	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-04-17 13:51:16 -07:00
David Harris	a413b5c6ca	Merge pull request #251 from masonadams25/main ... Removed redundent expression to increase coverage	2023-04-17 12:37:27 -07:00
Mason Adams	56575cb45e	Removed redundent expression to increase coverage	2023-04-17 14:13:26 -05:00
David Harris	64fe318cb0	merged coverage exclusions	2023-04-17 10:17:48 -07:00
Diego Herrera Vicioso	16fd17be39	Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc	2023-04-15 23:13:39 -07:00
Sydeny	0dc50536ef	trimming comments on fctrl bug fixes	2023-04-15 00:48:32 -07:00
Ross Thompson	30e3d2cdce	Merge pull request #233 from AlecVercruysse/coverage3 ... Full I$ coverage	2023-04-14 22:15:11 -05:00
Alec Vercruysse	4d9aa72877	replace instances of code duplication for i$ exclusions w/commands	2023-04-14 17:10:39 -07:00
Limnanthes Serafini	49e025bd48	Final small fix	2023-04-14 14:15:52 -07:00
Limnanthes Serafini	2c20079a46	indent fix	2023-04-14 14:14:34 -07:00
Limnanthes Serafini	b3976daccd	More cleanup	2023-04-13 21:34:50 -07:00
Limnanthes Serafini	b80a540c73	More cleanup	2023-04-13 21:02:30 -07:00
Limnanthes Serafini	53847269da	More changes	2023-04-13 21:02:15 -07:00
Limnanthes Serafini	0b6ce1b031	Some cleanup	2023-04-13 21:01:57 -07:00
David Harris	48de682ea8	Merged coverage-exclusions	2023-04-13 18:15:23 -07:00
David Harris	5066cd99ab	Merge pull request #237 from SydRiley/main ... fctrl coverage at 100% after removing redundancies from conditionals	2023-04-13 17:10:46 -07:00
Limnanthes Serafini	95586abe09	Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim	2023-04-13 16:54:16 -07:00
Limnanthes Serafini	034c289a36	Misc typo and indent fixing.	2023-04-13 16:54:15 -07:00
David Harris	11434f05e2	Starting fdivsqrt cleanup	2023-04-13 16:53:33 -07:00
Sydeny	2b8891cefd	Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu.	2023-04-13 16:27:53 -07:00
Alec Vercruysse	680aee7e07	Merge branch 'main' into coverage3	2023-04-12 16:00:15 -07:00
Alec Vercruysse	01f2417524	cachefsm exclude icache logic without code reuse	2023-04-12 15:57:45 -07:00
Alec Vercruysse	cc3b2bf435	Cachefsm gate LRUWriteEn with ~FlushStage	2023-04-12 13:32:36 -07:00
Sydeny	f9566299a0	fctrl coverage at 100% after removing redundancies from conditional statements	2023-04-12 13:07:30 -07:00
Ross Thompson	10be07857c	Merge pull request #229 from davidharrishmc/dev ... Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…	2023-04-12 12:21:03 -05:00
Alec Vercruysse	1cb6e1751b	Merge branch 'main' into coverage3	2023-04-12 09:34:09 -07:00
David Harris	6b05a71152	Removed unnecessary start term from initialization muxes to simplify and improve coverage	2023-04-12 03:34:01 -07:00
David Harris	463a1e2b33	Fixed fdivsqrt to avoid going from done to busy without going through idle first	2023-04-12 02:48:40 -07:00
Limnanthes Serafini	65d29306ef	Merge branch 'openhwgroup:main' into cachesim	2023-04-12 01:34:45 -07:00
Alec Vercruysse	0ed3e80ee0	only assign ClearDirtyWay for read-write caches	2023-04-12 01:15:35 -07:00
Alec Vercruysse	4cbb9bcec6	refactor cachefsm to get full coverage ... I had to exclude i$ states in coverage-exclusions-rv64gc.do, but it's referred to by scope, which should be pretty robust	2023-04-12 01:15:35 -07:00
Alec Vercruysse	a1bbcd5e8a	Coverage and readability improvements to LRUUpdate logic ... The genvar stuff was switched to readable names to make it easier to understand for the first time. In the LRUUpdate logic for loop, a special case was added for simpler logic in the case of the root node, to hit coverage.	2023-04-12 01:15:35 -07:00
Alec Vercruysse	5b8c6f070e	Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE ... Some address options are only used in the D$ case.	2023-04-12 01:15:35 -07:00
Alec Vercruysse	7c9f68e984	Remove FlushStage Logic from CacheLRU ... For coverage. LRUWriteEn is gated by FlushStage in cache.sv, so removing the signal completely avoids future confusion. Update cache.sv to reflect cacheLRU edit.	2023-04-12 01:15:35 -07:00
Alec Vercruysse	68a01cb0f8	Exclude (FlushStage & SetValidWay) condition for RO caches ... Spent a long time trying to find a way to see if this condition was possible, only to become relativly convinced that it isn't. Basically, since RO cache writes only happen after a long period of stall for the bus access, there's no way a flushD can be active at the same time as a RO cache write. TrapM causes a FlushD, but interrupts are gated by the "commited" logic and the exception pipeline stalls. I feel like its worth keeping the logic to be safe so I've chosen to exclude it rather than explicitely remove it.	2023-04-12 01:15:35 -07:00
Limnanthes Serafini	e5ead0f5b8	Minor logic cleanup (will elaborate in PR)	2023-04-11 19:29:39 -07:00
Alexa Wright	fb517163f5	Excluded coverage for misaligned instructions	2023-04-10 23:18:25 -07:00
Ross Thompson	81074a822a	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-04-09 12:19:44 -05:00
Kevin Thomas	f7838b869b	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-04-08 22:56:20 -05:00
David Harris	7affe2bdca	Waived coverage on BTB memory with byte write enables tied high	2023-04-07 21:56:49 -07:00
David Harris	2f4074b9c2	Improved RAS predictor coverage by eliminating unreachable StallM term	2023-04-07 21:37:12 -07:00
David Harris	5cdd3d57c7	Commented WFI non-flush in writeback stage of hazard unit	2023-04-07 21:27:13 -07:00
David Harris	9394389fec	Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed	2023-04-07 20:43:28 -07:00
David Harris	19c39628fa	Division cleanup	2023-04-06 21:42:34 -07:00
David Harris	6db65f30b1	Simplified integer division preprocessing in fdivsqrt	2023-04-06 16:43:28 -07:00
David Harris	7ad05d9a42	Removed redundant stall signal to get spill coverage	2023-04-06 14:07:50 -07:00
Jacob Pease	b796b1b492	Build doesn't work. AXI Crossbar has problems.	2023-04-06 16:01:58 -05:00
Ross Thompson	07b946bc75	Fixed syntax error.	2023-04-06 15:10:55 -05:00
Ross Thompson	4407d3310c	Added note about strange vivado behavior not inferring block ram.	2023-04-06 15:09:35 -05:00
Ross Thompson	ee4cf5e94d	Similifed the no byte write enabled version of the sram model.	2023-04-06 14:18:41 -05:00
Kevin Thomas	a588a9eb5d	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-04-06 12:38:41 -05:00
David Harris	4e3af7bca7	Merge pull request #211 from ross144/main ... Fixes the issue introduced by the fix for issue 203	2023-04-05 21:50:32 -07:00
Ross Thompson	e531b0103e	Fixed wally64/32priv test hangup. ... The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.	2023-04-05 23:13:45 -05:00
Kevin Thomas	d7188d6d9c	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-04-05 17:43:43 -05:00
Ross Thompson	7cdd12a40a	Merge pull request #206 from AlecVercruysse/coverage2 ... i$ coverage improvements	2023-04-05 17:29:35 -05:00
Alec Vercruysse	ac3569d75c	Update ram1p1rwe (ce & we) coverage exlusion explanation	2023-04-05 14:54:58 -07:00
Kevin Thomas	4d30aff198	Formating white space	2023-04-05 15:30:55 -05:00
Kevin Thomas	5ac49fa31f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-04-05 15:04:12 -05:00
Ross Thompson	da9cf02ba0	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-04-05 14:55:12 -05:00
Alec Vercruysse	570e86afc3	Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE ... To increase coverage. Read-only caches do not have flushes since they do not have dirty bits.	2023-04-05 11:48:18 -07:00
Alec Vercruysse	54df581ce6	make Cache Flush Logic dependent on !READ_ONLY_CACHE ... read-only caches do not have flush logic since they do not have to deal with dirty bits.	2023-04-05 11:48:18 -07:00
Alec Vercruysse	3419ef3651	remove ClearValid from cache ... The cachefsm hardwired ClearValid logic to zero. This signal might've been added to potentially add extra functionality later. Unless that functionality is added, however, it negatively impacts coverage. If the goal is to maximize coverage, this signal should be removed and only added when it becomes necessary.	2023-04-05 11:48:18 -07:00
Alec Vercruysse	81125d3180	change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe ... the byte write-enables were always tied high, so we can use RAM without byte-enable to increase coverage.	2023-04-05 11:48:18 -07:00
Alec Vercruysse	782feb6161	turn off ce coverage for ram1p1rwe ... According to the textbook, the cache memory chip enable, `CacheEn`, is only lowered by the cachefsm with it is in the ready state and a pipeline stall is asserted. For read only caches, cache writes only occur in the state_write_line state. So there is no way that a write would happen while the chip enable is low. Removing the chip-enable check from this memory to increase coverage would be a bad idea since if anyone else uses this ram, the behaviour would be differently than expected. Instead, I opted to turn off coverage for this statement. Since this ram, which does not have a byte enable, is used exclusively by read-only caches right now, this should not mistakenly exclude coverage for other cases, such as D$.	2023-04-05 11:48:18 -07:00
Alec Vercruysse	8b6b96012d	add ram1p1rwe for read-only cache ways (remove byte-enable) ... - increases coverage	2023-04-05 11:48:18 -07:00
Alec Vercruysse	2553321158	fix typo in cachway setValid input comment	2023-04-05 11:48:18 -07:00
Alec Vercruysse	9df246e5de	put cacheLRU coverage explanation on another line ... the `: explanation` syntax was not working	2023-04-05 11:48:18 -07:00
Alec Vercruysse	af113c7268	Exclude CacheLRU log2 function from coverage	2023-04-05 11:48:18 -07:00
Ross Thompson	394f2d65f2	Progress on bug 203.	2023-04-05 13:20:04 -05:00
Kevin Thomas	0c80067d45	Minor change with the IFU in the decompress module, in the compressed instruction truth table. ... The truth table is already fully covered, removed redundant last case checking	2023-04-05 10:27:52 -05:00
David Harris	4552f9cf8c	Fixed WFI to commit when an interrupt occurs	2023-04-04 09:32:26 -07:00
Ross Thompson	52d1c19509	Merge pull request #194 from davidharrishmc/dev ... Bit manipulation support in ImperasDV. Test improvements.	2023-04-04 09:13:27 -05:00
Kevin Kim	0a1adecf8a	Merge branch 'openhwgroup:main' into zbc_optimize	2023-04-03 23:45:49 -07:00
Kevin Kim	acebdeeb81	reduced mux3 to mux2 for input signal to clmul	2023-04-03 22:53:46 -07:00
David Harris	64679654ff	Merged priv.S edits	2023-04-03 18:07:14 -07:00
Sydeny	a0ecd83c47	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-04-03 13:41:55 -07:00
Ross Thompson	91e4e64f3d	Merge pull request #178 from AlecVercruysse/coverage ... Improve I$ coverage by simplifying logic	2023-04-03 14:22:46 -05:00
David Harris	4e2d80476e	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-04-03 06:13:16 -07:00
Sydeny	981e5bd5f6	Manual merge for fctrl.sv, fpu.S, and ifu.S files	2023-04-03 01:55:23 -07:00
Sydeny	17d41b4d52	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-04-03 01:54:27 -07:00
Sydney Riley	55655157ae	expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions.	2023-04-02 23:51:34 -07:00
Kevin Kim	b38d34b925	Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup	2023-04-02 21:14:35 -07:00
Kevin Kim	8252706691	removed comparator flag to ALU	2023-04-02 21:14:31 -07:00
Kevin Kim	238e97d379	signal renaming on bitmanip alu and alu	2023-04-02 18:42:41 -07:00
Kevin Kim	f175f7e927	changed signal names on clmul and zbc to match book	2023-04-02 18:28:09 -07:00
David Harris	db542543cb	Coverage improvement: ieu, hazard, priv	2023-03-31 08:34:34 -07:00
David Harris	fd0c9e973d	Coverage improvements in ieu, hazard units	2023-03-31 08:33:46 -07:00
Marcus Mellor	fd08ff2e60	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-31 10:29:10 -05:00
Mike Thompson	9abfef7c39	Merge pull request #179 from davidharrishmc/dev ... Fixed broken regression: privileged tests and build root	2023-03-31 10:56:27 -04:00
Marcus Mellor	219176db9b	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-31 09:54:02 -05:00
Marcus Mellor	09b2cd304f	Address comments in openhwgroup/cvw#180	2023-03-31 09:51:33 -05:00
Kevin Kim	2c6359b097	only pass in relevant comparator flag to ALU	2023-03-30 19:15:33 -07:00
Kevin Kim	1e88ec7eac	Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup	2023-03-30 19:04:41 -07:00
Kevin Kim	27a5c9c5d6	Merge branch 'openhwgroup:main' into bitmanip_cleanup	2023-03-30 19:04:36 -07:00
Marcus Mellor	3afd963a9e	Disable coverage for branches tested in fpu.s	2023-03-30 19:44:55 -05:00
David Harris	da53f240d3	Refactored InstrValidNotFlushed into CSR Write signals	2023-03-30 17:06:09 -07:00
David Harris	406bb22b6a	Started factoring out InstrValidNotFlushed from CSRs	2023-03-30 14:56:19 -07:00
David Harris	f34218666a	fctrl updated and buildroot working again	2023-03-30 13:17:15 -07:00
David Harris	9129c3ac22	fctrl continued cleanup	2023-03-30 13:07:39 -07:00
David Harris	01c5d58a64	fctrl continued cleanup	2023-03-30 13:05:56 -07:00
David Harris	b2a102ce79	Started to clean up fctrl	2023-03-30 12:57:14 -07:00
Alec Vercruysse	4b58bb55f2	Make entire cache write path conditional on READ_ONLY_CACHE	2023-03-30 10:32:40 -07:00
Kip Macsai-Goren	3805cf993a	unnecessary comments cleanup	2023-03-29 19:32:57 -07:00
Kip Macsai-Goren	491ef14b71	Resolved ImperasDV receiving incorrect cause values	2023-03-29 15:04:56 -07:00
Alec Vercruysse	d507f85190	icache coverage improvements by simplifying logic	2023-03-29 13:04:00 -07:00
David Harris	9d8f9e4428	Reduced number of bits in mcause and medeleg registers	2023-03-29 07:02:09 -07:00
David Harris	59f825a54b	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-29 06:19:10 -07:00
David Harris	f2c24b869d	Simplified fctrl	2023-03-28 21:13:48 -07:00
Alec Vercruysse	46df428e56	add check for legal funct3 for IW instructions	2023-03-28 15:59:48 -07:00
David Harris	92a7e86942	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-28 14:33:18 -07:00
Ross Thompson	d0f8db7939	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-28 16:31:50 -05:00
David Harris	6849eeae0c	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-28 14:27:08 -07:00
Ross Thompson	366a96a0fc	Possible fix for issue 148. ... I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU. I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss. This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.	2023-03-28 14:47:08 -05:00
Kevin Kim	582c561cb1	comment formatting	2023-03-28 11:40:19 -07:00
Kevin Kim	926f3d2a5a	Merge branch 'openhwgroup:main' into bitmanip_cleanup	2023-03-28 11:31:18 -07:00
David Harris	64bf9510ad	Added support (untested) for half and quad conversions	2023-03-28 10:53:06 -07:00
David Harris	36a0d35ae5	fixed fp->fp conversions	2023-03-28 10:35:41 -07:00
David Harris	4e50cc3379	support more fp -> fp conversions	2023-03-28 10:28:01 -07:00
David Harris	074fd1d9c3	Fixed fmv decoder	2023-03-28 10:21:33 -07:00
Ross Thompson	e49cf8a028	Merge pull request #169 from davidharrishmc/dev ... PMP Fix to issue 132	2023-03-28 11:49:00 -05:00
David Harris	2e5c50e24a	Fixed RV32 tests after PMP fix	2023-03-28 08:35:23 -07:00
David Harris	e8904411ce	Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests	2023-03-28 06:58:17 -07:00
David Harris	2e238c15aa	CSRS privileged coverage test	2023-03-28 04:37:56 -07:00
Ross Thompson	d91188c86e	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-27 11:55:19 -05:00
David Harris	9b7e5cec1f	Removed unnecessary monitor	2023-03-27 09:52:38 -07:00
Ross Thompson	d9691c1542	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-27 10:22:48 -05:00
Lee Moore	4bb7dadc00	Merge branch 'openhwgroup:main' into add-linux	2023-03-27 09:44:13 +01:00
Kevin Kim	5d3260de63	removed unnecessary signal indices	2023-03-26 20:06:55 -07:00
Kevin Kim	f6ce03730a	removed unneccesary input signal from zbb	2023-03-26 19:39:49 -07:00
Ross Thompson	ca4b058373	Modified plic and uart to remove async reset. This removes vivado critical warning.	2023-03-24 20:37:48 -05:00
Ross Thompson	0afba56927	Updated GPIO signal names to reflect book.	2023-03-24 18:55:43 -05:00
Ross Thompson	af8f1fd036	Renamed controllerinputstage to controllerinput to match book.	2023-03-24 17:57:02 -05:00
David Harris	0b0d954e7f	Merged ross's spacing fixes	2023-03-24 15:47:26 -07:00
David Harris	092d34373f	Merge pull request #159 from ross144/main ... Renamed signal to match book	2023-03-24 15:34:59 -07:00
Ross Thompson	46b1bca4fc	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
Jacob Pease	2d0199a354	Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore	2023-03-24 17:01:27 -05:00
Ross Thompson	b5a58502d0	Replaced tabs -> spaces cache.	2023-03-24 15:15:38 -05:00
Ross Thompson	b518177a45	Updated EBU to replace tabs with spaces.	2023-03-24 15:01:38 -05:00
Kevin Kim	b70ab0fa5a	Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu	2023-03-24 11:52:51 -07:00
David Harris	4b9b20bce0	Shifter capitalization	2023-03-24 09:01:07 -07:00
Ross Thompson	47f8e847f0	Renamed ebu signal.	2023-03-24 10:51:04 -05:00
David Harris	89954df49b	Query about CondExtA	2023-03-24 08:35:33 -07:00
David Harris	21424d0f86	Shifter sign simplification and capitalization	2023-03-24 08:27:30 -07:00
David Harris	cb261731f2	FPU detect illegal instructions	2023-03-24 08:12:32 -07:00
David Harris	f1e87c5e69	Start of EBU coverage tests	2023-03-24 08:12:02 -07:00
David Harris	576545e328	ALUControl Elimination	2023-03-24 08:10:48 -07:00
David Harris	f648be8ee2	Merged ALUOp into ALUControl to simplify ALU mux	2023-03-24 07:28:42 -07:00
David Harris	89479391ca	Simplified rotate source to shifter	2023-03-24 06:49:26 -07:00
David Harris	e8d6073eca	BMU simplifications	2023-03-24 06:18:06 -07:00
David Harris	3bdb176253	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-24 05:59:48 -07:00
Kevin Kim	4c73f0fffd	minor formatting	2023-03-23 22:28:21 -07:00
Kevin Kim	5a19934511	comments	2023-03-23 22:22:25 -07:00
Kevin Kim	ae162a2694	removed redundant signals ... -fixed some comments too	2023-03-23 22:20:37 -07:00
Kevin Kim	9c457e3af4	bitmanip alu submodule passes lint and regression	2023-03-23 21:56:03 -07:00
Kevin Kim	443e64bef2	more progress. Failing regression	2023-03-23 20:42:49 -07:00
Kevin Kim	2a2aa0470a	Merge branch 'openhwgroup:main' into bitmanip-alu	2023-03-23 19:53:50 -07:00
David Harris	c8ea5afe25	Removed unnecessary XZero from fdivsqrt	2023-03-23 17:25:59 -07:00
David Harris	f2864c7305	Merged BMU	2023-03-23 17:24:40 -07:00
Kevin Kim	8e67c64e2c	fixed rori rv32 bug	2023-03-23 16:06:46 -07:00
Kevin Kim	51d691215f	more progress on bitmanip alu modularization	2023-03-23 16:02:38 -07:00
David Harris	4e1bf6fbe0	Improved IEU and bitmanip test coverage	2023-03-23 14:24:41 -07:00
Kevin Kim	519a0452a5	started bitmanip alu modularization	2023-03-23 14:02:28 -07:00
David Harris	121d1cea62	Added csrwrites.S test case for privileged tests	2023-03-23 10:55:32 -07:00
Kevin Kim	a084b8ca31	Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip	2023-03-22 10:34:19 -07:00
Kevin Kim	fd00e386b5	remove outdated	2023-03-22 10:34:17 -07:00
Kevin Kim	1eb96e2221	Merge branch 'openhwgroup:main' into bit-manip	2023-03-22 10:33:15 -07:00
Kevin Kim	efa9f09864	updated header comments to indicate chapter 15	2023-03-22 10:31:21 -07:00
Kevin Kim	f7a915a71a	remove helper python script	2023-03-22 10:27:59 -07:00
Kevin Kim	fce62fc213	formatting	2023-03-22 10:26:04 -07:00
Kevin Kim	e9f90050d5	min/max mux optimize	2023-03-22 10:25:54 -07:00
Kevin Kim	c8a5514ca5	formatting	2023-03-22 10:14:12 -07:00
eroom1966	259fbc8d77	support linux	2023-03-22 17:10:32 +00:00
David Harris	e03a533775	Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault	2023-03-22 06:29:30 -07:00
David Harris	80fc851332	Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0	2023-03-22 04:41:57 -07:00
David Harris	a1eccf37dc	Fix Issue 145	2023-03-22 04:33:14 -07:00
Kevin Kim	3f46dff23e	Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip	2023-03-21 11:20:05 -07:00
David Harris	df9ce03252	Renamed intdivrestoring to div	2023-03-21 05:51:02 -07:00
David Harris	718844012e	Renamed intdivrestoring to div	2023-03-20 16:22:06 -07:00
Kevin Kim	72a8b25272	formatting	2023-03-20 14:25:05 -07:00
Kevin Kim	2ad807728c	more structural mux changes	2023-03-20 14:23:54 -07:00
Kevin Kim	4ecfa1bad3	added bitmanip 64 tests to updated regression script ... + alu structural mux changes	2023-03-20 14:19:39 -07:00
Kevin Kim	5056eb404c	formatting	2023-03-20 13:09:49 -07:00
Kevin Kim	82d52f892b	Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip	2023-03-20 13:06:10 -07:00
David Harris	18737b58df	formatting cleanup	2023-03-20 12:45:10 -07:00
Kevin Kim	b394e343f6	format + min/max structural mux	2023-03-20 09:37:57 -07:00
David Harris	cd0240d938	Eliminate transitions to FLUSH and WRITEBACK in cachefsm for READ_ONLY_CACHE	2023-03-19 10:41:47 -07:00
David Harris	4c6f539449	Removed flq from LLEN=64	2023-03-19 10:25:04 -07:00
David Harris	ff22520d9e	Added comments about PMP checker fixes when test cases will be ready to initialize PMP before entering user mode	2023-03-19 05:46:34 -07:00
David Harris	4cde207958	Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.	2023-03-18 10:10:58 -07:00
David Harris	f53b2f6e1f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-18 09:24:37 -07:00
David Harris	6922298f21	Replaced FenceM with InvalidateICacheM for event counting of fence.i	2023-03-18 09:24:31 -07:00
Ross Thompson	3d37d2769a	Book updates.	2023-03-14 13:09:50 -05:00
Ross Thompson	3cae6ca90f	Updated NextAdr to NextSet.	2023-03-13 14:54:13 -05:00
Ross Thompson	c190444fa2	Updated CAdr to CacheSet.	2023-03-13 14:53:00 -05:00
Ross Thompson	ada099c58b	Changes BTA to BPBTA.	2023-03-12 14:36:46 -05:00
Ross Thompson	a5523400ae	Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.	2023-03-12 13:21:22 -05:00
Kevin Kim	0d0d3b981e	more checks in bitmanip decode	2023-03-10 17:17:24 -08:00
Kevin Kim	9b4f3219db	formatting	2023-03-10 14:32:01 -08:00
Kevin Kim	c380b0816d	removed redundant convinvb signal	2023-03-10 14:18:24 -08:00
Kevin Kim	dcaf9de228	removed redundant condinvb mux	2023-03-10 14:17:38 -08:00
David Harris	f411803bc4	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-10 12:47:30 -08:00
David Harris	33fa7e4706	Simplified SLT and SLTU code in ALU	2023-03-09 15:14:52 -08:00
Kevin Kim	f29e8932a2	more comprehensive illegal b instr. check	2023-03-09 12:44:51 -08:00
Kevin Kim	f335d08bbf	fixed bmu bug ... - accidentally deleted count instruction decode	2023-03-09 12:35:42 -08:00
Ross Thompson	68b437ce92	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-09 13:29:38 -06:00
Kevin Kim	260dcc8b96	Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip	2023-03-08 16:22:47 -08:00
Kevin Kim	7002221dec	cleaner bmu decode logic	2023-03-08 16:22:43 -08:00
Ross Thompson	4db17cde2f	Updated testbench to record coremark performance counters. ... Added comment about mtval probably not being correct for compressed instructions.	2023-03-08 17:11:27 -06:00
kipmacsaigoren	2337e2ae16	Merge branch 'openhwgroup:main' into bit-manip	2023-03-07 21:29:03 -08:00
David Harris	88c3a61cd7	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-07 14:49:23 -08:00
Kevin Kim	0ca530fffd	Merge branch 'bit-manip' into illegal_specific	2023-03-07 14:07:59 -08:00
Kevin Kim	f29bbe5f69	Merge branch 'openhwgroup:main' into illegal_specific	2023-03-07 14:06:22 -08:00
Kevin Kim	4bb43892f9	alu formatting	2023-03-07 14:01:47 -08:00
Kevin Kim	26cb1857f3	specifc instruction handling for B's ... - Added BALUSrcBD, BaseALUSrcB for distinguishing between base instruction I/IW and Bitmanip instruction I/IW	2023-03-07 13:58:08 -08:00
kipmacsaigoren	24f0f34aff	Merge branch 'openhwgroup:main' into priv-tests	2023-03-07 13:46:55 -08:00
Kip Macsai-Goren	f28a284e5e	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-03-07 13:45:04 -08:00
Kip Macsai-Goren	2ec3c741ef	Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip	2023-03-07 13:44:51 -08:00
Kip Macsai-Goren	f178c90c02	Merge branch 'main' of github.com:kipmacsaigoren/cvw into bit-manip	2023-03-07 13:44:19 -08:00
Kevin Kim	bd9b9970f5	Merge remote-tracking branch 'origin' into illegal_specific	2023-03-07 11:30:36 -08:00
Kevin Kim	6d146a7e20	formatting	2023-03-07 10:57:52 -08:00
Kevin Kim	833e7bd2af	shifter sign generation logic optimize	2023-03-07 10:57:06 -08:00
David Harris	77ba71be71	editorconfig to specify tabs/spaces. Fixed some tabs. Turn off coverage to speed up simulation	2023-03-07 06:31:40 -08:00
Kevin Kim	81198ce6f6	reverted backing to working version	2023-03-07 00:29:58 -08:00
Kevin Kim	5637897dce	reverted to working version	2023-03-07 00:28:07 -08:00
Ross Thompson	6d4e28fdf2	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-06 22:29:27 -06:00
Ross Thompson	e448cd54ef	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-06 18:39:15 -06:00
Ross Thompson	a6b851a672	Renamed signals to be consistent with textbook.	2023-03-06 18:29:31 -06:00
Ross Thompson	31fcc0daf7	Renamed PCFSpill to PCSpillF.	2023-03-06 17:50:57 -06:00
Ross Thompson	473ed2b475	Renamed InstrFirstHalf to InstrFirstHalfF.	2023-03-06 17:48:57 -06:00
Ross Thompson	fdfb80a818	Renamed ebuarbfsm to ebufsmarb to match figures.	2023-03-06 17:47:55 -06:00
David Harris	7ecf4cdea8	Fixed bug about rv64 shifts only using 6 bits of funct7	2023-03-06 13:10:51 -08:00
David Harris	7e0c96cdcc	Simplified decoder default to illegal instruction	2023-03-06 11:21:11 -08:00
David Harris	c2efdbdbbb	More detailed decoding of load/store/branch/jump	2023-03-06 11:15:48 -08:00
David Harris	a56557d847	Improved decoding illegal instructions in controller	2023-03-06 11:02:42 -08:00
Kevin Kim	c7d1e35d4a	structural changes in cnt.sv	2023-03-06 06:44:15 -08:00
Kevin Kim	e67b02136c	formatting	2023-03-06 06:20:25 -08:00
Kevin Kim	ee66b5fb4a	formatting ... - reverted back to ALUResult signal in alu.sv	2023-03-06 06:19:01 -08:00
Kevin Kim	8f3acedec8	formatted files	2023-03-06 05:52:08 -08:00
Kevin Kim	fb529e1640	updated license header	2023-03-06 05:41:53 -08:00
Kevin Kim	e80c1248a2	bug fix	2023-03-05 15:20:48 -08:00
Kevin Kim	3dbdf3d579	extend unit structural mux	2023-03-05 15:09:02 -08:00
Kevin Kim	696cfb6949	zbb result select mux structural	2023-03-05 14:57:30 -08:00
Kevin Kim	2ae32f75b5	zbc input mux structural	2023-03-05 14:26:31 -08:00
Kevin Kim	77d8f10574	revA signals to cnt, zbb	2023-03-05 14:26:24 -08:00
Kevin Kim	7836bc1e37	ALU changes ... - added PreShiftAmt signal for shadd - condinvB now muxes from B instead of mask	2023-03-05 14:06:24 -08:00
Kevin Kim	0f2360f0d7	bug in bctrl ... - deleted the min/minu decoding for some reason.	2023-03-04 23:56:33 -08:00
Kevin Kim	6b25c64a1f	BSelect from OH encoding to Binary	2023-03-04 23:19:31 -08:00
Kevin Kim	a293c350ba	alu pre-shift ... -changed ALU pre shift logic to use a 2 bit shifter instead of mux	2023-03-04 23:07:06 -08:00
Kevin Kim	7512e55699	added python script ... -I've been using this python script to make quick changes to the bitmanip controller	2023-03-04 22:54:32 -08:00
Kevin Kim	294e024c9b	Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip	2023-03-04 22:44:09 -08:00
Kevin Kim	9494cf9340	removed rotate signal in datapath and instead packed into the new BALUControl Signal ... - BALUControl contains Rotate, Mask, PreShift signals to select from the respective generation muxes in the ALU	2023-03-04 22:44:03 -08:00
Kip Macsai-Goren	a38f7cc8a1	added reset values to stime and stimecmp registers	2023-03-04 15:06:15 -08:00
Kip Macsai-Goren	4cede344a1	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-03-04 14:43:12 -08:00
Kevin Kim	f5dca0bf4f	zbc result mux is now structural	2023-03-04 09:22:21 -08:00
Kevin Kim	72de867e65	Rotate signal now gets generated in bmu ctrl	2023-03-03 22:57:49 -08:00
Kevin Kim	b315066b03	license comments	2023-03-03 21:52:34 -08:00
Kevin Kim	0403cfd41a	removed redundant signals in controller	2023-03-03 21:52:25 -08:00
Kevin Kim	8dd39fbcfb	b controller generates comparison signed flag and controller branch signed logic updated accordingly	2023-03-03 17:12:29 -08:00
Ross Thompson	da74ed0369	Merge pull request #126 from davidharrishmc/dev ... ImperasDV setup	2023-03-03 18:01:32 -06:00
David Harris	876c33da5f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-03 15:54:42 -08:00
Kevin Kim	5e01f86bc5	sltD signal debug. Passes regression	2023-03-03 12:44:33 -08:00
Kevin Kim	c836eea17c	sltD logic optimize	2023-03-03 12:35:40 -08:00
Kevin Kim	d6f8c1dd29	Merge branch 'bctrlmigrate' of https://github.com/kipmacsaigoren/cvw into bctrlmigrate	2023-03-03 09:54:08 -08:00
Kevin Kim	1c55d4a8d5	Merge branch 'openhwgroup:main' into bctrlmigrate	2023-03-03 09:53:59 -08:00
Kevin Kim	422b428cba	removed outdated b-signals in controller	2023-03-03 08:45:42 -08:00
Kevin Kim	9cad890c1a	comments to bctrl	2023-03-03 08:41:47 -08:00
Kevin Kim	19410b4196	migrated B-subarith logic into b controller	2023-03-03 08:40:29 -08:00
Kevin Kim	2c3271dd62	began subarith configurability optimization in controller	2023-03-03 08:27:11 -08:00
Ross Thompson	0cb5369351	Renamed BTB misprediction to BTA.	2023-03-03 00:18:34 -06:00
Ross Thompson	5b5677ccb8	Added divide cycle counter.	2023-03-02 23:59:52 -06:00
Ross Thompson	aabb454d1c	Added the i and d cache cycle counters.	2023-03-02 23:54:56 -06:00
Ross Thompson	cfca77172e	Added fence counter.	2023-03-02 23:29:20 -06:00
Ross Thompson	f32f8c109a	Added csr write counter, sfence vma counter, interrupt counter, and exception counter.	2023-03-02 23:21:29 -06:00
Ross Thompson	a313b10912	Added store stall to performance counters.	2023-03-02 23:10:54 -06:00
Ross Thompson	2dd693a3b3	Reordered performance counters and added space for new ones.	2023-03-02 23:04:31 -06:00
David Harris	316b8b2250	Refactored Floating point division special case detection to avoid spurious trigger on Y for sqrt)	2023-03-02 20:00:47 -08:00
Kevin Kim	b21ca2fba0	bug fix, more elegant logic changes in controller	2023-03-02 16:00:56 -08:00
Kevin Kim	c9bd37c92b	formatting	2023-03-02 15:28:43 -08:00
Kevin Kim	910eeea3ff	removed main instruction decoder dependence on bmu controller	2023-03-02 15:28:33 -08:00
Kevin Kim	05b329dd6a	added bitmanip illegal instruction signal	2023-03-02 15:09:55 -08:00
Kevin Kim	3e8e633a56	zbc comments	2023-03-02 13:52:00 -08:00
Kevin Kim	b0307f5082	formatted bmu decoder	2023-03-02 13:45:15 -08:00
Kevin Kim	24b0b83d52	moved ALUControlD into configurable block	2023-03-02 12:17:03 -08:00
Kevin Kim	0f60505179	moved SubArith and RegWriteE into configurable block	2023-03-02 12:15:57 -08:00
Kevin Kim	b81a5e4452	added BRegWriteE signal	2023-03-02 12:15:22 -08:00
Kevin Kim	5e10720bed	rename shifternew to shifter	2023-03-02 11:45:32 -08:00
Kevin Kim	cf324510f3	zbc input select mux optimize	2023-03-02 11:43:05 -08:00
Kevin Kim	657719220a	zbc select mux optimization	2023-03-02 11:40:29 -08:00
Kevin Kim	e62a752522	fixed controller lint, changed byte unit mux select name and input width	2023-03-02 11:36:12 -08:00
Kevin Kim	a5e2e24320	removed redundant zbs	2023-03-02 11:22:09 -08:00
Ross Thompson	b98e007a53	Cleaned up branch predictor performance counters.	2023-03-01 17:05:42 -06:00
David Harris	5c8c50adba	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-01 11:18:05 -08:00
David Harris	23775c6d67	Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA	2023-03-01 11:18:00 -08:00
Ross Thompson	90b2f0a652	Set bp to use instruction class prediction by default.	2023-03-01 11:52:42 -06:00
Ross Thompson	dea6b643a6	Branch predictor cleanup. ... I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.	2023-03-01 11:24:24 -06:00
Ross Thompson	03a6679ba0	More btb cleanup.	2023-03-01 10:47:00 -06:00
Ross Thompson	554e7d0973	Minor fix to btb.	2023-03-01 10:45:40 -06:00
Ross Thompson	a6917d07f3	Name cleanup.	2023-02-28 17:48:58 -06:00
Kip Macsai-Goren	58ab6ec805	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-02-28 14:41:51 -08:00
Kip Macsai-Goren	f63748f097	Merge remote-tracking branch 'origin' into bit-manip	2023-02-28 14:39:57 -08:00
Ross Thompson	4c0e7f297a	Found the performance bug with the branch predictor btb power saving update.	2023-02-28 15:57:34 -06:00
Ross Thompson	2ebe600f54	Name changes to reflect diagrams.	2023-02-28 15:37:25 -06:00
Ross Thompson	be4823f7dd	Undid the btb update as it reduces performance.	2023-02-28 15:21:56 -06:00
Kevin Kim	df0d75034b	bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG]	2023-02-28 12:09:35 -08:00
Kevin Kim	b61d881c1b	added BRegWrite, BW64, BALUOp signals to bctrl and controller ... -TODO: Main decode in bmuctrl must assert these 3 signals	2023-02-28 11:54:10 -08:00
Kevin Kim	692e406976	changed shifter source select signal name	2023-02-28 11:41:40 -08:00
Kevin Kim	1506d50c63	rename result back to ALUResult in ALU	2023-02-28 07:27:34 -08:00
Ross Thompson	9dd3379744	This icpred and btb changes are causing a performance issue.	2023-02-27 20:00:50 -06:00
Ross Thompson	544abe2819	Modified the BTB to save power by not updating when the prediction is unchanged.	2023-02-27 17:37:29 -06:00
Ross Thompson	bc5aecf948	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-27 09:48:03 -06:00
David Harris	cf8b5f0783	Added support for ZMMUL	2023-02-27 07:29:53 -08:00
Ross Thompson	318189e5e6	Signal name changes.	2023-02-27 00:39:19 -06:00
David Harris	f40352e82b	hptw typo fix	2023-02-26 19:38:34 -08:00
Ross Thompson	c89812b2d4	Branch predictor cleanup.	2023-02-26 21:28:36 -06:00
David Harris	e9ad6ae057	Simplified Access fault logic in HPTW	2023-02-26 18:50:37 -08:00
David Harris	2d7145901b	StoreAmo faults are generated instead of load faults on AMO operations	2023-02-26 18:35:10 -08:00
Ross Thompson	e8c5e5b5ff	Create module for instruction class prediction and decoding.	2023-02-26 20:20:30 -06:00
Ross Thompson	3964ce3309	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-02-26 19:58:24 -06:00
David Harris	21b28fd1bb	Renamed DAPageFault to UpdateDA	2023-02-26 17:51:45 -08:00
David Harris	4274071333	renamed UpperBitsUnequalPageFault to UpperBitsUnequal	2023-02-26 17:32:34 -08:00
David Harris	06bd4783af	moved tlb to subdirectory	2023-02-26 17:31:03 -08:00
David Harris	c774b44116	Moved TLB into subdirectory of MMU	2023-02-26 17:28:05 -08:00
Ross Thompson	72be4318b8	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-02-26 12:06:06 -06:00
David Harris	dc447ed5ed	Removed unneeded TLBFlush from TLBMiss	2023-02-26 10:04:16 -08:00
David Harris	54b8e7c629	Access faults are geted by ~TLBMiss rather than ~(Translate & ~TLBHit)	2023-02-26 09:58:34 -08:00
David Harris	35653a18b7	Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED	2023-02-26 09:38:32 -08:00
David Harris	f31764c3e1	Renamed DAPageFault to HPTWDAPageFault in hptw to avoid name conflict with DAPageFault from tlbcontrol	2023-02-26 07:12:43 -08:00
David Harris	fe161f6bde	Fixed missing assign when SSTC is not supported	2023-02-26 07:12:13 -08:00
David Harris	8895114152	Fixed SSTC being unusable in M-MODE without Status.TM. Disable STIMECMP registers when SSTC_SUPPORTED = 0	2023-02-26 06:30:43 -08:00
Ross Thompson	7f8034013d	PHT was enabled using the wrong ~flush and ~stall.	2023-02-24 22:57:32 -06:00
Ross Thompson	eb9dc7e67d	gshare cleanup.	2023-02-24 22:55:51 -06:00
Ross Thompson	9df05f0b3d	More signal renames.	2023-02-24 19:56:55 -06:00
Ross Thompson	8bd4a4c35b	Renamed signals to match new figures.	2023-02-24 19:51:47 -06:00
Kevin Kim	f5d3e0e8a0	removed old shifter	2023-02-24 17:33:47 -08:00
Ross Thompson	f95f326b3d	Renamed signals to match figure 10.18.	2023-02-24 19:22:14 -06:00
Kevin Kim	601c6fcdc4	removed now-redundant zero-extend mux in alu	2023-02-24 17:14:12 -08:00
Kevin Kim	1d4200e3a3	took sign extension out of shifter	2023-02-24 17:09:56 -08:00
Ross Thompson	40a164a8da	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-24 18:50:35 -06:00
Ross Thompson	4031b89f18	Possible fix to btb performance issue.	2023-02-24 18:36:41 -06:00
Ross Thompson	ea8cb7dd78	Cleanup.	2023-02-24 18:20:42 -06:00
Ross Thompson	a14dcaa241	Completed critical path gshare fix.	2023-02-24 18:02:00 -06:00
Ross Thompson	31d6531af2	Prep to fix gshare critical path.	2023-02-24 17:54:48 -06:00
Ross Thompson	5db56460b9	Modified btb forwarding logic to reduce critical path.	2023-02-24 17:47:43 -06:00
Kevin Kim	00a0170b30	optimized mux to shifter, passes rv32/64i	2023-02-24 12:09:34 -08:00
Kip Macsai-Goren	f77d8206ec	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-02-24 09:28:24 -08:00
David Harris	adfc01fc5a	Fixed special cases of address decoder and documented better	2023-02-24 07:52:46 -08:00
Kevin Kim	8b6d699857	small optimization to condzext select	2023-02-23 21:57:28 -08:00
Ross Thompson	2920179435	Major cleanup of bp.	2023-02-23 16:19:03 -06:00
Ross Thompson	fa49de8391	Partial replacement of InstrClassX with {JalX, RetX, JumpX, and BranchX}.	2023-02-23 15:55:34 -06:00
Kip Macsai-Goren	cb3990c77d	Merge remote-tracking branch 'upstream/main' into main	2023-02-23 13:33:45 -08:00
Ross Thompson	8503982328	Branch predictor cleanup.	2023-02-23 15:15:14 -06:00
Ross Thompson	403b2b7be1	Moved more branch predictor logic into the performance counter block.	2023-02-23 15:14:56 -06:00
Ross Thompson	526f046fb0	Added if generate around bp logic only used with performance counters.	2023-02-23 14:39:31 -06:00
Ross Thompson	2d919fa9e3	Renamed PCPredX to BTAX.	2023-02-23 14:33:32 -06:00
Kip Macsai-Goren	67f83cda7f	Fixed lint errors on zero and pop count. All of regression passes	2023-02-22 20:25:51 -08:00
Kip Macsai-Goren	ba3bfdf68b	Manual attempt to merge with upstream changes	2023-02-22 19:42:30 -08:00
Kip Macsai-Goren	cc47bd8bea	Merge remote-tracking branch 'upstream/main' into main	2023-02-22 15:47:54 -08:00
Ross Thompson	c736d7c1f3	Fixed bug in basic gshare.	2023-02-22 12:54:46 -06:00
Ross Thompson	849856034b	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-22 09:11:57 -06:00
Ross Thompson	5dde3af22e	Oups. Turns out dc_shell does not like string parameters. ... Switched gshare to use an integer parameter to select between gshare and global.	2023-02-22 09:11:46 -06:00
Kip Macsai-Goren	d668c563f4	Merge remote-tracking branch 'upstream/main' into main	2023-02-21 14:48:41 -08:00
Kevin Kim	35bd4f7219	added individual zb tests in tests.vh and testbench ... - also minor alu/controller configurability changes	2023-02-21 11:52:05 -08:00
David Harris	f0566173e6	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-02-21 09:58:18 -08:00
David Harris	b59df0fca7	Fixed Issue #65 fmv sign selection. Sign needs to come from most significant bit of raw X source without doing NaN Box fixes first.	2023-02-21 09:57:57 -08:00
David Harris	a445e53e8d	Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.	2023-02-21 09:32:17 -08:00
Ross Thompson	7f0d64d0a6	Fixed typo in the global branch predictor.	2023-02-20 18:48:02 -06:00
Ross Thompson	2c2c1b5221	Cleanup branch predictor files.	2023-02-20 18:45:45 -06:00
Ross Thompson	7df3a84060	Renamed branch predictors and consolidated global and gshare predictors.	2023-02-20 18:42:37 -06:00
Ross Thompson	6eefa5b1e3	Fixed another bug in the btb.	2023-02-20 17:54:22 -06:00
Ross Thompson	d2b7047744	Fixed forwarding bug in the BTB.	2023-02-20 17:03:45 -06:00
Ross Thompson	fdd007a903	Found a bug where the d and i cache misses were not recorded in the performance counters.	2023-02-20 16:00:29 -06:00
Ross Thompson	545af7697f	Simiplified BTB.	2023-02-20 15:39:42 -06:00
David Harris	1028fd1053	Removed test code that broke LSU	2023-02-20 12:42:46 -08:00
David Harris	da61d11de1	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-02-20 11:28:15 -08:00
David Harris	36b2d530c4	Merge pull request #98 from ross144/main ... New gshare implementation	2023-02-20 11:27:47 -08:00
David Harris	801f4a68b7	Extraction script updates to match new reports names	2023-02-20 10:16:45 -08:00
David Harris	4cc8448b16	Removed unused and incomplete ROM macro instantations	2023-02-20 05:59:57 -08:00
David Harris	626715befd	Fixed IROM size parameters	2023-02-20 05:32:43 -08:00
David Harris	472c7da399	New expression for BTB_SIZE to avoid error during sky90 synthesis	2023-02-20 04:02:00 -08:00
Ross Thompson	4db249ca5d	Simplified BTB by removing the valid bit. the instruction class provides the equivalent information.	2023-02-19 23:53:20 -06:00
Ross Thompson	407d9e7b4a	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-19 22:54:27 -06:00
Ross Thompson	0f98cfe5b4	Simplified branch predictor.	2023-02-19 22:49:48 -06:00
David Harris	d07c6386b2	Added BTB_SIZE parameter independent of BPRED_SIIZE	2023-02-19 20:13:50 -08:00
David Harris	20ced0653c	Parameterized btb to depend on BPRED_SIZE	2023-02-19 19:59:07 -08:00
Kip Macsai-Goren	65a5b86dd8	Merge remote-tracking branch 'upstream/main' into main	2023-02-19 16:37:18 -08:00
David Harris	5287c54278	Adjusted DTIM to always be 512B independent of XLEN	2023-02-19 16:14:38 -08:00
David Harris	00d54cfe6c	PMP checker size check to avoid spurious warnings	2023-02-19 16:08:23 -08:00
David Harris	fa0406b554	Moved conditional instantiation outside pmpchecker	2023-02-19 15:31:00 -08:00
David Harris	8db49c83c4	Disabled W64M register for RV32	2023-02-19 07:03:31 -08:00
David Harris	527566c38a	Fixed RAM instantiations	2023-02-19 06:31:41 -08:00
Ross Thompson	89aa57e25e	Possibly much better branch predictor implemention. ... The complexity is significantly reduced.	2023-02-19 00:17:37 -06:00
Kevin Kim	0f876c3111	B DONE (for now) ... - datapath passes along comparator flag to alu - controllers and zbb handle min/max instructions	2023-02-18 22:12:55 -08:00
Ross Thompson	9f997eb5d0	Minor fix.	2023-02-18 23:55:46 -06:00
Kevin Kim	2319661b10	controlleres and zbb handle byte instructions	2023-02-18 21:06:55 -08:00
Kevin Kim	e7339902ae	alu and controllers handle andn, orn, xnor	2023-02-18 20:57:07 -08:00
Kevin Kim	59e9c7c747	added logic to handle sign/zero extend instructions	2023-02-18 20:32:40 -08:00
Kevin Kim	ad63699aac	fixed ctlzw bug in count unit	2023-02-18 20:12:30 -08:00
Kevin Kim	ecfcad20a0	zbb handles count instructions	2023-02-18 20:12:17 -08:00
Kevin Kim	543dc1e36a	fixed bmuctrl decode bug	2023-02-18 20:11:50 -08:00
Kevin Kim	446327215d	updated comments in bmuctrl	2023-02-18 19:57:10 -08:00
Kevin Kim	baff2c9362	rotate instructions now handled in ZBB unit	2023-02-18 19:56:54 -08:00
Kevin Kim	e4085764e7	removed redundant decode logic in bmuctrl	2023-02-18 19:50:36 -08:00
Kevin Kim	f18cd53dee	began ZBB integration into ieu	2023-02-18 19:44:14 -08:00
Kevin Kim	5f56f72bb1	bmuctrl handles roriw	2023-02-18 16:26:16 -08:00
Kip Macsai-Goren	9c3aa55349	merge upstream synth changes	2023-02-18 14:35:19 -08:00
David Harris	92d4acf118	Removed unused PredInstrClassE register from bpred	2023-02-18 05:59:25 -08:00
David Harris	1af99c7aee	Removed unused weq0M register fron fdivsqrtpostproc	2023-02-18 05:57:39 -08:00
David Harris	adc22235be	Fixed issue #57 of sign selection for improperly NaN-boxed number	2023-02-18 05:34:40 -08:00
David Harris	7923d32c3a	Fixed unpacking of illegal NaN box. Fixed issue #56 of sign injection NaN	2023-02-18 05:25:38 -08:00
Kevin Kim	2ccbde9d09	configured shifter in alu	2023-02-17 21:58:49 -08:00
Kevin Kim	f85c1058ff	shifter bug fix ... - roli not passing unless I keep the MSB (instead of inverting) of truncated offset	2023-02-17 21:58:26 -08:00
Kevin Kim	77fc40149f	controller supports some rotates	2023-02-17 21:57:34 -08:00
Kevin Kim	5e7ed8804f	bmuctrl supports some rotates	2023-02-17 21:57:19 -08:00
David Harris	63a6567ed3	Created PostBox signal to NaN-box malformed NaNs of excess length. Fixes Issue #55	2023-02-17 20:51:43 -08:00
Kevin Kim	9af0ffe3a9	added zero extend, pre-shift mux to ALU	2023-02-17 20:15:12 -08:00
Kevin Kim	cad0973b6b	more elegant ZBA logic in controller	2023-02-17 20:14:47 -08:00
Kevin Kim	88d7c3b1f2	bmuctrl handles .uw instructions	2023-02-17 20:14:13 -08:00
David Harris	154d7eb9ef	Fixed RAM bugs and refactored with read taking place after clock edge rather than before.	2023-02-17 19:14:38 -08:00
Kevin Kim	01f3cc2838	controller supports ZBA instructions	2023-02-17 16:44:16 -08:00
Kevin Kim	b09d942d60	removed Funct7 in Execute Stage	2023-02-17 16:12:09 -08:00
David Harris	daf2f822c2	Memory synthesis updates	2023-02-17 15:33:49 -08:00
David Harris	3f2f48ddc6	Continue fixing memory macros for synthesis	2023-02-17 15:15:37 -08:00
Ross Thompson	ae8b01b8d4	Renamed globalhistory predictor.	2023-02-17 16:08:34 -06:00
Ross Thompson	2661ec97d8	Fixed global history predictor.	2023-02-17 16:05:48 -06:00
Ross Thompson	a98a85f144	More updates.	2023-02-17 15:53:49 -06:00
Ross Thompson	1d9335c934	Updated global history predictor.	2023-02-17 15:53:15 -06:00
David Harris	aba29f6cc8	Synthesis with memories	2023-02-17 13:51:05 -08:00
Ross Thompson	e0a8974c7d	Fixed a branch predictor performance issue.	2023-02-17 15:37:03 -06:00
Kevin Kim	a1570a88c9	bmuctrl checks for illegal zbs-style instructions	2023-02-17 12:54:08 -08:00
Kevin Kim	370ff54875	bctrl bug fix ... - bctrl decodes shift immediate instructions properly	2023-02-17 11:16:29 -08:00
Kevin Kim	aba4eb80d4	alu bug fix ... - condmaskb piped in correctly instead of b	2023-02-17 11:02:07 -08:00
Kevin Kim	07eaf146c2	alu looks at BSelect, added BSelect one hot signal	2023-02-17 09:51:49 -08:00
Ross Thompson	c97fa02300	Merge branch 'main' of github.com:ross144/cvw	2023-02-17 10:58:16 -06:00
Ross Thompson	3398c5156b	Fixed bug with branch predictor.	2023-02-17 10:57:50 -06:00
Kevin Kim	323d14f9d9	added alu changes to previous commit	2023-02-17 08:22:13 -08:00
Kevin Kim	44c9612a5c	added BSelect Signal ... - BSelect [3:0] is a one hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction	2023-02-17 08:21:55 -08:00
Kevin Kim	ada6023a41	comments	2023-02-17 07:53:14 -08:00
Kevin Kim	ab542a5bc3	comments	2023-02-17 07:52:54 -08:00
Kevin Kim	290fcd1789	comment formatting	2023-02-17 07:51:28 -08:00
Kevin Kim	5b341ac3a7	alu handles ALU select instead of funct3	2023-02-17 07:51:10 -08:00
Kevin Kim	ff365de54a	added BMU controll	2023-02-17 07:50:59 -08:00
Kevin Kim	f0c81247e4	Added ALUSelect signal into datapath, ieu, controller	2023-02-17 07:50:45 -08:00
David Harris	0d2baed943	Reverted lab3 changes in dev branch	2023-02-16 18:10:05 -08:00
David Harris	26ea8b03c3	Merge branch 'lab3_2023' of https://github.com/openhwgroup/cvw into dev	2023-02-16 17:57:51 -08:00
David Harris	33eb5423cb	Update datapath.sv	2023-02-16 17:53:31 -08:00
David Harris	113b124721	Update controller.sv	2023-02-16 17:52:44 -08:00
David Harris	43afa34338	Update alu.sv	2023-02-16 17:52:25 -08:00
Jacob Pease	45b264fa59	Merge branch 'main' of github.com:openhwgroup/cvw into boot	2023-02-16 17:36:26 -06:00
Ross Thompson	b62bacbac3	keep this commit off of cvw.	2023-02-16 11:05:24 -06:00
David Harris	5b370bdc0f	Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.	2023-02-16 07:37:12 -08:00
Kevin Kim	921a32faf9	added comments to zbc units	2023-02-15 17:42:32 -08:00
Kevin Kim	50f0262498	zbc configurability and select mux	2023-02-15 17:39:37 -08:00
Kevin Kim	cd13913f07	controller forwards funct7 ... - started the bmu controll register	2023-02-15 17:38:12 -08:00
Kevin Kim	8feeaa5e94	zbc and carry-less multiply work properly	2023-02-15 17:37:09 -08:00
James Stine	a3aeff2703	Update if-then-else for ram items	2023-02-15 18:12:12 -06:00
Kevin Kim	2eb8721843	continued ZBC integration into ALU	2023-02-15 09:35:07 -08:00
Ross Thompson	c6920ab08e	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-15 11:29:39 -06:00
Kevin Kim	2a58a86371	added ALUResult Signal	2023-02-15 09:13:10 -08:00
Kevin Kim	27817c5b1d	controller passes funct7 from decode to execute	2023-02-14 16:06:10 -08:00
Kevin Kim	857097282c	git	2023-02-14 16:03:26 -08:00
Kevin Kim	420a0209dd	Merge branch 'tmp' into main	2023-02-14 13:12:57 -08:00
Kevin Kim	7b7957594e	removed unncessary stuff	2023-02-14 13:07:03 -08:00
Kevin Kim	1a209aac21	reverted back to I tests working	2023-02-14 13:06:31 -08:00
Kevin Kim	bcea347370	added ALU result select mux for B instructions	2023-02-13 17:38:00 -08:00
Kevin Kim	1364ac2a14	controller handles bclr	2023-02-13 16:57:05 -08:00
Ross Thompson	911023f441	Merge branch 'main' of github.com:ross144/cvw	2023-02-13 18:54:07 -06:00
Ross Thompson	fc3baa6846	Updated gshare (no speculation) to have better performance.	2023-02-13 18:52:52 -06:00
Kevin Kim	2679f06a00	Shadd instructions pass tests	2023-02-13 16:36:17 -08:00
Ross Thompson	f3c8c6e60a	More fixeds to global history.	2023-02-13 18:08:51 -06:00
Ross Thompson	6ea830cf44	Fixed global history predictor.	2023-02-13 18:08:13 -06:00
Ross Thompson	3847d9e39a	Updated global history predictor.	2023-02-13 18:07:32 -06:00
Ross Thompson	1ab2d0d19b	Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now.	2023-02-13 17:57:05 -06:00
Ross Thompson	c18ac35332	Created copy of gshare. I think there may be a simpler implementation.	2023-02-13 17:29:51 -06:00
Ross Thompson	10b45ed6c7	Further branch predictor improvements.	2023-02-13 17:23:56 -06:00
Ross Thompson	1cfdd201a5	Partial improvement.	2023-02-13 17:10:24 -06:00
Ross Thompson	0165fd54b4	Hacked commit. Fixes the gshare bugs introduced last week. ... Need to recover the good changes in the next commit.	2023-02-13 16:14:17 -06:00
Kevin Kim	02a7dc45f0	ALU lint fixes	2023-02-13 14:01:51 -08:00
Kevin Kim	ed6a0466ad	ALU configurability changes ... -stuff that was ZBA supported was in ZBB so I changed that	2023-02-13 14:00:06 -08:00
Kevin Kim	c9e6b9aeef	edited controller so that add.uw passes tests	2023-02-13 13:49:46 -08:00
Kevin Kim	cf09bbff5f	alu add.uw needs w64 to be false	2023-02-13 13:49:35 -08:00
Ross Thompson	716fbca2b1	Partial fix for gshare bugs from the last two weeks.	2023-02-13 11:57:25 -06:00
Ross Thompson	51158e94ba	Removed another bit from btb class.	2023-02-12 11:33:43 -06:00
Kevin Kim	19c8fa75f5	simulation runs-- clmul doesn't pass lint with xor tree	2023-02-11 21:22:33 -08:00
Kevin Kim	67db085b24	lint fixes	2023-02-11 21:13:10 -08:00
Kevin Kim	c7dbb49208	zbb, zbs, cnt lint fixes	2023-02-11 20:41:52 -08:00
Kevin Kim	016634d842	fixed byte unit lints	2023-02-11 20:25:34 -08:00
Kevin Kim	3653ea61b5	fixed lints in cnt	2023-02-11 20:22:42 -08:00
Kevin Kim	2dfbf15ff9	fixed typo in LZC	2023-02-11 19:59:03 -08:00
Kevin Kim	52ca8fa691	popcnt passes lint	2023-02-11 19:19:38 -08:00
Kevin Kim	2fefc3019e	clmul passes lint	2023-02-11 19:16:13 -08:00
Ross Thompson	91fc883f6a	More simplifications to the BP.	2023-02-10 17:09:35 -06:00
Ross Thompson	6fbca64eb7	Experimental branch prediction optimization.	2023-02-10 15:45:56 -06:00
Kip Macsai-Goren	f95038551f	fixed small errors to get regression to run with bit manip supported.	2023-02-10 10:37:06 -08:00
Kip Macsai-Goren	137dd890a0	Merge remote-tracking branch 'upstream/main' into main	2023-02-10 10:01:14 -08:00
Ross Thompson	eafb406c9e	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-10 10:38:39 -06:00
Ross Thompson	ca0eb5a591	Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic.	2023-02-10 10:33:10 -06:00
Ross Thompson	91427ed72d	RAS and RAS documentation now consistent.	2023-02-10 09:06:51 -06:00
Ross Thompson	2d7749db7f	Updated globalhistory predictor.	2023-02-09 14:48:02 -06:00
Kevin Kim	f58a2b70a0	Include Funct7 in execute ... - Modifed datapath to support funct7 in execute - Modified controller to pass on Funct7 - all lints pass	2023-02-09 19:18:54 +00:00
Kevin Kim	76a8f2d3d3	added W64 zbb input signal in alu	2023-02-09 19:07:22 +00:00
Kevin Kim	17bd001057	modified zbb to account for cnt module change	2023-02-09 16:45:37 +00:00
Kevin Kim	5b5f9a2784	modified cnt for zbb to mux inputs	2023-02-09 16:45:22 +00:00