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https://github.com/openhwgroup/cvw
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Update csrc.sv
Program clean up
This commit is contained in:
Harshini Srinath
GitHub
parent
a2645dd576
commit
02a11278fc
@ -1,5 +1,3 @@
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///////////////////////////////////////////
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// csrc.sv
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//
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@ -31,57 +29,57 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csrc import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallE, StallM,
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input logic FlushM,
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input logic InstrValidNotFlushedM, LoadStallD, StoreStallD,
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input logic CSRMWriteM, CSRWriteM,
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input logic BPDirPredWrongM,
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input logic BTAWrongM,
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input logic RASPredPCWrongM,
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input logic IClassWrongM,
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input logic BPWrongM, // branch predictor is wrong
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input logic [3:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic ICacheStallF,
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input logic DCacheStallM,
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input logic sfencevmaM,
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input logic InterruptM,
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input logic ExceptionM,
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input logic InvalidateICacheM,
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input logic DivBusyE, // integer divide busy
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input logic FDivBusyE, // floating point divide busy
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic clk, reset,
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input logic StallE, StallM,
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input logic FlushM,
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input logic InstrValidNotFlushedM, LoadStallD, StoreStallD,
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input logic CSRMWriteM, CSRWriteM,
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input logic BPDirPredWrongM,
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input logic BTAWrongM,
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input logic RASPredPCWrongM,
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input logic IClassWrongM,
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input logic BPWrongM, // branch predictor is wrong
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input logic [3:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic ICacheStallF,
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input logic DCacheStallM,
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input logic sfencevmaM,
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input logic InterruptM,
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input logic ExceptionM,
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input logic InvalidateICacheM,
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input logic DivBusyE, // integer divide busy
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input logic FDivBusyE, // floating point divide busy
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic [P.XLEN-1:0] CSRWriteValM,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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input logic [63:0] MTIME_CLINT,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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input logic [63:0] MTIME_CLINT,
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output logic [P.XLEN-1:0] CSRCReadValM,
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output logic IllegalCSRCAccessM
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output logic IllegalCSRCAccessM
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);
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localparam MHPMCOUNTERBASE = 12'hB00;
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localparam MTIME = 12'hB01; // this is a memory-mapped register; no such CSR exists, and access should faul;
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localparam MHPMCOUNTERBASE = 12'hB00;
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localparam MTIME = 12'hB01; // this is a memory-mapped register; no such CSR exists, and access should faul;
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localparam MHPMCOUNTERHBASE = 12'hB80;
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localparam MTIMEH = 12'hB81; // this is a memory-mapped register; no such CSR exists, and access should fault
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localparam MHPMEVENTBASE = 12'h320;
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localparam HPMCOUNTERBASE = 12'hC00;
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localparam HPMCOUNTERHBASE = 12'hC80;
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localparam TIME = 12'hC01;
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localparam TIMEH = 12'hC81;
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localparam MTIMEH = 12'hB81; // this is a memory-mapped register; no such CSR exists, and access should fault
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localparam MHPMEVENTBASE = 12'h320;
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localparam HPMCOUNTERBASE = 12'hC00;
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localparam HPMCOUNTERHBASE = 12'hC80;
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localparam TIME = 12'hC01;
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localparam TIMEH = 12'hC81;
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logic [4:0] CounterNumM;
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logic [P.XLEN-1:0] HPMCOUNTER_REGW[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] HPMCOUNTERH_REGW[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] HPMCOUNTER_REGW[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] HPMCOUNTERH_REGW[P.COUNTERS-1:0];
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logic LoadStallE, LoadStallM;
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logic StoreStallE, StoreStallM;
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logic [P.COUNTERS-1:0] WriteHPMCOUNTERM;
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logic [P.COUNTERS-1:0] CounterEvent;
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logic [P.COUNTERS-1:0] WriteHPMCOUNTERM;
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logic [P.COUNTERS-1:0] CounterEvent;
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logic [63:0] HPMCOUNTERPlusM[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] NextHPMCOUNTERM[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] NextHPMCOUNTERM[P.COUNTERS-1:0];
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genvar i;
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// Interface signals
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@ -95,16 +93,16 @@ module csrc import cvw::*; #(parameter cvw_t P) (
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if(P.QEMU) begin: cevent // No other performance counters in QEMU
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assign CounterEvent[P.COUNTERS-1:3] = 0;
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end else begin: cevent // User-defined counters
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assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
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assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions
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assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
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assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong
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assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction
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assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target
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assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address
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assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
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assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions
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assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
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assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong
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assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction
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assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target
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assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address
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assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong
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assign CounterEvent[11] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed.
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assign CounterEvent[12] = StoreStallM; // Store Stall
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assign CounterEvent[11] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed.
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assign CounterEvent[12] = StoreStallM; // Store Stall
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assign CounterEvent[13] = DCacheAccess & InstrValidNotFlushedM; // data cache access
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assign CounterEvent[14] = DCacheMiss; // data cache miss. Miss asserted 1 cycle at start of cache miss
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assign CounterEvent[15] = DCacheStallM; // d cache miss cycles
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