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Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.

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This commit is contained in:
Ross Thompson 2023-05-31 16:51:00 -05:00
parent 76fd76c155
commit 1ceea51d8b
5 changed files with 87 additions and 31 deletions
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2
config/shared/parameter-defs.vh
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@ -76,7 +76,7 @@ parameter cvw_t P = '{
// *** definitely need to fix this.
// it thinks we are casting from the enum type to BPRED_TYPE.
BPRED_TYPE : BPRED_TYPE,
/* verilator lint_off ENUMVALUE */
/* verilator lint_on ENUMVALUE */
BPRED_SIZE : BPRED_SIZE,
BPRED_NUM_LHR : BPRED_NUM_LHR,
BTB_SIZE : BTB_SIZE,

4
sim/verilate
View File

@ -7,8 +7,8 @@ verilator=`which verilator`
basepath=$(dirname $0)/..
#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
for config in rv64gc; do
echo "$config linting..."
if !($verilator --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "$config simulating..."
if !($verilator --timescale "1ns/1ns" --timing --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/testbench/common/*.sv $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi

19
src/wally/wallypipelinedsoc.sv
View File

@ -26,22 +26,19 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
//import cvw::*; // global CORE-V-Wally parameters
module wallypipelinedsoc import cvw::*; (
module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic reset_ext, // external asynchronous reset pin
output logic reset, // reset synchronized to clk to prevent races on release
// AHB Interface
input logic [AHBW-1:0] HRDATAEXT,
input logic [P.AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic HSELEXT,
// outputs to external memory, shared with uncore memory
output logic HCLK, HRESETn,
output logic [PA_BITS-1:0] HADDR,
output logic [AHBW-1:0] HWDATA,
output logic [XLEN/8-1:0] HWSTRB,
output logic [P.PA_BITS-1:0] HADDR,
output logic [P.AHBW-1:0] HWDATA,
output logic [P.XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
@ -64,14 +61,12 @@ module wallypipelinedsoc import cvw::*; (
);
// Uncore signals
logic [AHBW-1:0] HRDATA; // from AHB mux in uncore
logic [P.AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP; // response from AHB
logic MTimerInt, MSwInt;// timer and software interrupts from CLINT
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
logic MExtInt,SExtInt; // from PLIC
`include "parameter-defs.vh"
// synchronize reset to SOC clock domain
synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
@ -83,7 +78,7 @@ module wallypipelinedsoc import cvw::*; (
);
// instantiate uncore if a bus interface exists
if (BUS_SUPPORTED) begin : uncore
if (P.BUS_SUPPORTED) begin : uncore
uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,

3
testbench/common/instrNameDecTB.sv
View File

@ -250,7 +250,10 @@ module instrNameDecTB(
else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
else if (funct7[6:2] == 5'b10100) name = "FEQ";
else name = "ILLEGAL";
/* verilator lint_off CASEOVERLAP */
// *** RT: definitely take a look at this. This overlaps with 10'b1010011_000
10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
/* verilator lint_on CASEOVERLAP */
else if (funct7[6:2] == 5'b00001) name = "FSUB";
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";

90
testbench/testbench.sv
View File

@ -26,6 +26,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
`include "config.vh"
`include "tests.vh"
`define PrintHPMCounters 0
@ -33,7 +34,12 @@
`define I_CACHE_ADDR_LOGGER 0
`define D_CACHE_ADDR_LOGGER 0
import cvw::*;
module testbench;
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off WIDTHEXPAND */
parameter DEBUG=0;
parameter TEST="none";
@ -42,7 +48,8 @@ module testbench;
parameter SIGNATURESIZE = 5000000;
int test, i, errors, totalerrors;
int test, errors, totalerrors;
logic [`PA_BITS-1:0] i;
logic [31:0] sig32[0:SIGNATURESIZE];
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
logic [`XLEN-1:0] testadr, testadrNoBase;
@ -66,6 +73,8 @@ module testbench;
logic HCLK, HRESETn;
logic [`XLEN-1:0] PCW;
`include "parameter-defs.vh"
string ProgramAddrMapFile, ProgramLabelMapFile;
integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
@ -190,7 +199,7 @@ module testbench;
assign HRDATAEXT = 0;
end
if(`FPGA) begin : sdcard
if(P.FPGA) begin : sdcard
sdModel sdcard
(.sdClk(SDCCLK),
.cmd(SDCCmd),
@ -204,7 +213,7 @@ module testbench;
assign SDCDat = '0;
end
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
@ -239,9 +248,8 @@ module testbench;
// not initialized the compare results in an 'x' which propagates through
// the design.
if (TEST == "coremark")
for (i=MemStartAddr; i<MemEndAddr; i = i+1)
for (i=MemStartAddr; i<MemEndAddr; i = i+1)
dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0;
// read test vectors into memory
pathname = tvpaths[tests[0].atoi()];
/* if (tests[0] == `IMPERASTEST)
@ -249,18 +257,29 @@ module testbench;
else pathname = tvpaths[1]; */
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
else memfilename = {pathname, tests[test], ".elf.memfile"};
if (`FPGA) begin
if (P.FPGA) begin
string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
*/
// force sdc timers
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
*/
end else begin
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
*/
// *** replace this with above
$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
*/
end
if (riscofTest) begin
@ -273,7 +292,7 @@ module testbench;
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
// the addr of each label and fill the array. To expand, add more elements to this array
// and initialize them to zero (also initilaize them to zero at the start of the next test)
if(!`FPGA) begin
if(!P.FPGA) begin
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
$display("Read memfile %s", memfilename);
end
@ -365,10 +384,15 @@ module testbench;
errors = (i == SIGNATURESIZE+1); // error if file is empty
i = 0;
/* verilator lint_off INFINITELOOP */
/* verilator lint_off WIDTHXZEXPAND */
while (signature[i] !== 'bx) begin
/* verilator lint_on WIDTHXZEXPAND */
logic [`XLEN-1:0] sig;
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
*/
sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
errors = errors+1;
@ -399,10 +423,14 @@ module testbench;
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
else memfilename = {pathname, tests[test], ".elf.memfile"};
//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
*/
// *** replace this with the above
$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (riscofTest) begin
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
@ -421,6 +449,7 @@ module testbench;
end // always @ (negedge clk)
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
integer HPMCindex;
logic StartSampleFirst;
@ -503,7 +532,7 @@ module testbench;
end
end
end
*/
// track the current function or global label
@ -541,6 +570,7 @@ module testbench;
integer adrindex;
// local history only
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
if (`BPRED_TYPE == "BP_LOCAL_AHEAD" | `BPRED_TYPE == "BP_LOCAL_REPAIR") begin
always @(*) begin
if(reset) begin
@ -550,14 +580,19 @@ module testbench;
end
end
end
*/
always @(*) begin
if(reset) begin
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
testbench.dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
*/
end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
*/
end
end
end
@ -647,7 +682,9 @@ module testbench;
logic PCSrcM;
string LogFile;
logic resetD, resetEdge;
/* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed.
flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
*/
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
@ -686,6 +723,9 @@ module testbench;
end
end
/* verilator lint_on WIDTHTRUNC */
/* verilator lint_on WIDTHEXPAND */
endmodule
/* verilator lint_on STMTDLY */
@ -697,17 +737,25 @@ module DCacheFlushFSM
input logic start,
output logic done);
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off WIDTHEXPAND */
genvar adr;
logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
if(`DCACHE_SUPPORTED) begin
localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
//localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam numlines = DCACHE_WAYSIZEINBYTES*8/DCACHE_LINELENINBITS;
//localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam numways = DCACHE_NUMWAYS;
//localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam linebytelen = DCACHE_LINELENINBITS/8;
localparam linelen = DCACHE_LINELENINBITS;
//localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam sramlen = 128;
//localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
localparam cachesramwords = DCACHE_LINELENINBITS/sramlen;
localparam numwords = sramlen/`XLEN;
localparam lognumlines = $clog2(numlines);
localparam loglinebytelen = $clog2(linebytelen);
@ -772,6 +820,8 @@ module DCacheFlushFSM
end
end
flop #(1) doneReg(.clk, .d(start), .q(done));
/* verilator lint_on WIDTHTRUNC */
/* verilator lint_on WIDTHEXPAND */
endmodule
module copyShadow
@ -790,6 +840,8 @@ module copyShadow
output logic CacheDirty);
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off WIDTHEXPAND */
always_ff @(posedge clk) begin
if(start) begin
CacheTag = tag;
@ -800,9 +852,13 @@ module copyShadow
end
end
/* verilator lint_on WIDTHTRUNC */
/* verilator lint_on WIDTHEXPAND */
endmodule
task automatic updateProgramAddrLabelArray;
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off WIDTHEXPAND */
input string ProgramAddrMapFile, ProgramLabelMapFile;
inout integer ProgramAddrLabelArray [string];
// Gets the memory location of begin_signature
@ -821,5 +877,7 @@ task automatic updateProgramAddrLabelArray;
end
$fclose(ProgramLabelMapFP);
$fclose(ProgramAddrMapFP);
/* verilator lint_on WIDTHTRUNC */
/* verilator lint_on WIDTHEXPAND */
endtask