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Kevin Kim
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420a0209dd
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857097282c
109
src/ieu/alu.sv
109
src/ieu/alu.sv
@ -32,78 +32,31 @@
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module alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [2:0] ALUControl, // With Funct3, indicates operation to perform
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input logic [6:0] Funct7,
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input logic [6:0] Funct7, // Funct7 from execute stage
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input logic [2:0] Funct3, // With ALUControl, indicates operation to perform
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output logic [WIDTH-1:0] Result, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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// CondInvB = ~B when subtracting or inverted operand instruction in ZBB, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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logic [WIDTH-1:0] ZBBResult, ZBSResult;
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA, ALUResult; // Intermediate results
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; // Intermediate results
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logic Carry, Neg; // Flags: carry out, negative
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logic LT, LTU; // Less than, Less than unsigned
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logic W64; // RV64 W-type instruction
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logic SubArith; // Performing subtraction or arithmetic right shift
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logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops
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logic Asign, Bsign; // Sign bits of A, B
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logic InvB; // Is Inverted Operand Instruction (ZBB)
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logic Rotate; // Is rotate operation
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logic ZbaAdd; // Is ZBA Add Operation
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logic rotate;
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// Extract control signals from ALUControl.
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assign {W64, SubArith, ALUOp} = ALUControl;
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// Addition
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if (`ZBA_SUPPORTED)
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always_comb begin
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ZbaAdd = (Funct7 == 7'b0010000 | Funct7 == 7'b0000100);
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case({Funct7, Funct3, W64})
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11'b0010000_010_0: CondShiftA = {A[WIDTH-2:0], {1'b0}}; //sh1add
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11'b0010000_100_0: CondShiftA = {A[WIDTH-3:0], {2'b00}}; //sh2add
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11'b0010000_110_0: CondShiftA = {A[WIDTH-4:0], {3'b000}}; //sh3add
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11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw
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11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw
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11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b00}}; //sh2add.uw
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11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b000}}; //sh3add.uw
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default: CondShiftA = A;
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endcase
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end
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else begin
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assign CondShiftA = A;
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assign ZbaAdd = 0;
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end
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if (`ZBB_SUPPORTED)
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always_comb begin
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case ({Funct7,Funct3})
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10'b0100000_111: InvB = 1'b0; //andn
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10'b0100000_110: InvB = 1'b0; //orn
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10'b0100000_100: InvB = 1'b0; //xnor
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default: InvB = 1'b0;
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endcase
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casez ({Funct7, Funct3})
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10'b011000?_101: Rotate = 1'b1;
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10'b000010?_001: Rotate = 1'b0;
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10'b0110000_001: Rotate = 1'b1;
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default: Rotate = 1'b0;
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endcase
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end
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else begin
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assign InvB = 1'b0;
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assign Rotate = 1'b0;
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end
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assign CondInvB = (SubArith | InvB) ? ~B : B;
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assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
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assign CondInvB = SubArith ? ~B : B;
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assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
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// Shifts
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shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Rotate(Rotate), .Y(Shift));
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shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(rotate));
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// Condition code flags are based on subtraction output Sum = A-B.
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// Overflow occurs when the numbers being subtracted have the opposite sign
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@ -121,42 +74,18 @@ module alu #(parameter WIDTH=32) (
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// Select appropriate ALU Result
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always_comb
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if (~ALUOp | ZbaAdd) FullResult = Sum; // Always add for ALUOp = 0 (address generation) and ZBA
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else casez (Funct3) // Otherwise check Funct3
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ CondInvB; // xor
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3'b110: FullResult = A | CondInvB; // or
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3'b111: FullResult = A & CondInvB; // and
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if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation)
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else casez (Funct3) // Otherwise check Funct3
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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if (`ZBS_SUPPORTED)
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zbs #(WIDTH) zbs(.A, .B, .Funct7, .Funct3, .ZBSResult);
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else assign ZBSResult = 0;
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if (`ZBB_SUPPORTED)
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zbb #(WIDTH) zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult);
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else assign ZBBResult = 0;
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (WIDTH == 64) assign ALUResult = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign ALUResult = FullResult;
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if (`ZBB_SUPPORTED | `ZBA_SUPPORTED | `ZBS_SUPPORTED | `ZBC_SUPPORTED) begin
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always_comb
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casez({Funct7})
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7'b010010?: Result = ZBSResult;
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7'b001010?: Result = ZBSResult;
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default: Result = ALUResult;
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endcase
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end else begin
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assign Result = ALUResult;
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end
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endmodule
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if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign Result = FullResult;
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endmodule
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@ -149,7 +149,7 @@ module controller(
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ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo
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end else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED) | (Funct7D == 7'b0100100 & `ZBS_SUPPORTED))
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7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000)
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ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type
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else if (Funct7D == 7'b0000001 & `M_SUPPORTED)
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ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide
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@ -161,10 +161,7 @@ module controller(
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else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64)
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ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
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else
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if ((Funct7D == 7'b0000100 | Funct7D == 7'b0010000) & `ZBA_SUPPORTED)
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ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // adduw, sh1adduw, sh2adduw, sh3adduw
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
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7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
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7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
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@ -193,23 +190,13 @@ module controller(
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assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001);
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assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i
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if (`ZBA_SUPPORTED) begin
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// ALU Decoding is more comprehensive when ZBA is supported
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assign sltD = (Funct3D == 3'b010 & OpD == 7'b0010011);
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assign sltuD = (Funct3D == 3'b011 & OpD == 7'b0010011);
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assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
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assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
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assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
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assign ALUControlD = {W64D, SubArithD, ALUOpD};
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end else begin
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// ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
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assign sltD = (Funct3D == 3'b010);
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assign sltuD = (Funct3D == 3'b011);
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assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
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assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
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assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
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assign ALUControlD = {W64D, SubArithD, ALUOpD};
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end
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// ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
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assign sltD = (Funct3D == 3'b010);
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assign sltuD = (Funct3D == 3'b011);
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assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
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assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
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assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
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assign ALUControlD = {W64D, SubArithD, ALUOpD};
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// Fences
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// Ordinary fence is presently a nop
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@ -228,9 +215,9 @@ module controller(
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flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
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// Execute stage pipeline control register and logic
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flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE,
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{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD},
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{IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE});
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flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE,
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{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD},
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{IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE});
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// Branch Logic
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// The comparator handles both signed and unsigned branches using BranchSignedE
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@ -264,4 +251,4 @@ module controller(
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// the synchronous DTIM cannot read immediately after write
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// a cache cannot read or write immediately after a write
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assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD));
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endmodule
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endmodule
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