David Harris c6631ef808 Added N and PBMT bits to MMU PTE		2023-08-24 19:44:46 -07:00
..
cache	Fixed bug with the cbo.inval clearing already cleared lines.	2023-08-21 17:51:51 -05:00
ebu	Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.	2023-07-21 16:31:26 -05:00
fpu	Merge pull request #372 from davidharrishmc/dev	2023-07-31 11:28:28 -04:00
generic	Merge branch 'boot' into mergeBoot	2023-07-21 17:43:45 -05:00
hazard	MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.	2023-05-24 15:01:35 -05:00
ieu	Fixed cbo instruction decode.	2023-08-18 11:32:30 -05:00
ifu	Initial CMO implementation. Just adds control signals into the L1 caches.	2023-08-14 15:43:12 -05:00
lsu	Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.	2023-08-18 15:59:39 -05:00
mdu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
mmu	Added N and PBMT bits to MMU PTE	2023-08-24 19:44:46 -07:00
privileged	Added N and PBMT bits to MMU PTE	2023-08-24 19:44:46 -07:00
uncore	Cleaned up lint for plic_apb part select	2023-07-30 02:00:38 -07:00
wally	Merge branch 'boot' into mergeBoot	2023-07-21 17:43:45 -05:00
cvw.sv	Added N and PBMT bits to MMU PTE	2023-08-24 19:44:46 -07:00