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Merge pull request #313 from ross144/main

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Fix extraneous force in testbench which keep btb in reset.
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David Harris 2023-06-06 08:41:34 -07:00 committed by GitHub
commit 75dc86ddc0
2 changed files with 2 additions and 2 deletions
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2
src/privileged/csrc.sv
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@ -98,7 +98,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions
assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong
assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong
assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction
assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target
assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address

2
testbench/testbench.sv
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@ -554,7 +554,7 @@ module testbench;
always @(*) begin
if(reset) begin
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;