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Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.

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This commit is contained in:
David Harris 2023-04-22 12:22:45 -07:00
parent 063e41806e
commit 086556310c
4 changed files with 32 additions and 5 deletions
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7
sim/coverage-exclusions-rv64gc.do
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@ -31,11 +31,14 @@
do GetLineNum.do
# LZA (i<64) statement confuses coverage tool
# This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working
# DH 4/22/23: Exclude all LZAs
coverage exclude -srcfile lzc.sv
# FDIVSQRT has
# DH 4/22/23: FDIVSQRT can't go directly from done to busy again
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY
# DH 4/22/23: The busy->idle transition only occurs if a FlushE occurs while the divider is busy. The flush is caused by a trap or return,
# which won't happen while the divider is busy.
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE
### Exclude D$ states and logic for the I$ instance
# This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)

3
src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -63,10 +63,11 @@ module fdivsqrtfsm(
flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
always_ff @(posedge clk) begin
// coverage off: dh 4/22/23 FlushE doesn't seem to happen while fdivsqrt is busy
if (reset | FlushE) begin
// coverage on
state <= #1 IDLE;
end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
// end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE
step <= CyclesE;
if (SpecialCaseE) state <= #1 DONE;
else state <= #1 BUSY;

3
tests/coverage/WALLY-init-lib.h
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@ -63,6 +63,9 @@ trap_handler:
bgez t0, exception # if msb is clear, it is an exception
interrupt: # must be a timer interrupt
li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
li t1, 0x02004000 # MTIMECMP in CLINT
sd t0, 0(t1)
j trap_return # clean up and return
exception:

24
tests/coverage/fpu.S
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@ -28,7 +28,7 @@
main:
#bseti t0, zero, 14 # turn on FPU
bseti t0, zero, 14 # turn on FPU
csrs mstatus, t0
#Pull denormalized FP number from memory and pass it to fclass.S for coverage
@ -105,6 +105,25 @@ main:
# fcvt.w.q a0, ft0
# fcvt.q.d ft3, ft0
// fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives)
// This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes.
li t0, 0x3F812345 # random value slightly bigger than 1
li t1, 0x3F823456
fmv.w.x ft0, t0 # move int to fp register
fmv.w.x ft1, t1
li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
li t1, 0x02004000 # MTIMECMP in CLINT
sd t0, 0(t1)
csrsi mstatus, 0b1000 # enable interrupts with mstatus.MIE
li t1, 0x0200bff8 # read MTIME in CLINT
ld t0, 0(t1)
addi t0, t0, 11
li t1, 0x02004000 # MTIMECMP in CLINT
sd t0, 0(t1) # write mtime+10 to cause interrupt soon This is very touchy timing and is sensitive to cache line fetch latency
nop
fdiv.s ft2, ft1, ft0 # should get interrupted, triggering a flush
csrci mstatus, 0b1000 # disable interrupts with mstatus.MIE
# Completing branch coverage in fctrl.sv
.word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011
.word 0x40000053 // Line 145 All False Test case - illegal instruction?
@ -145,4 +164,5 @@ TestData2:
.word 0x7f800000 #INF
.int 0xbf800000 #FP -1.0
.int 0x7fa00000 #SNaN
.int 0x3fffffff #OverFlow Test
.int 0x3fffffff #OverFlow Test
DivTestData: