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Update atomic.sv
Program clean up
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@ -28,24 +28,24 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module atomic import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic reset,
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input logic StallW,
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input logic clk,
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input logic reset,
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input logic StallW,
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input logic [P.XLEN-1:0] ReadDataM, // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
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input logic [P.XLEN-1:0] IHWriteDataM, // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
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input logic [P.PA_BITS-1:0] PAdrM, // Physical memory address
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input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW
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input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size
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input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
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input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal
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input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation
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input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW
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input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size
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input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
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input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal
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input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation
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output logic [P.XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC
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);
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logic [P.XLEN-1:0] AMOResultM;
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logic MemReadM;
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logic MemReadM;
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amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
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