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Fixed bug about rv64 shifts only using 6 bits of funct7
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@ -127,13 +127,16 @@ module controller(
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// Be rigorous about detecting illegal instructions if CSRs or bit manipulation is supported
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// otherwise be cheap
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if (`ZICSR_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED) begin // Exact integer decoding
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if (`ZICSR_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED) begin:legalcheck // Exact integer decoding
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logic Funct7ZeroD, Funct7b5D, IShiftD, INoShiftD;
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logic Funct7ShiftZeroD, Funct7Shiftb5D;
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assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions
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assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub
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assign IShiftD = (Funct3D == 3'b001 & Funct7ZeroD) | (Funct3D == 3'b101 & (Funct7ZeroD | Funct7b5D)); // slli, srli, srai, or w forms
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assign INoShiftD = (Funct3D != 3'b001 & Funct3D != 3'b101);
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assign Funct7ShiftZeroD = (`XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD;
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assign Funct7Shiftb5D = (`XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D;
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assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms
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assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101));
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assign IFunctD = IShiftD | INoShiftD;
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assign RFunctD = ((Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) | Funct7ZeroD;
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assign MFunctD = (Funct7D == 7'b0000001) & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
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@ -143,7 +146,7 @@ module controller(
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((`XLEN == 64) & (Funct3D == 3'b011));
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assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches
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assign JFunctD = (Funct3D == 3'b000);
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end else begin
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end else begin:legalcheck2
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assign IFunctD = 1; // Don't bother to separate out shift decoding
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assign RFunctD = ~Funct7D[0]; // Not a multiply
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assign MFunctD = Funct7D[0] & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
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