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The Vivado-RISC-V SDC works. Wally is now booting through it.

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This commit is contained in:
Jacob Pease 2023-05-26 15:42:33 -05:00
parent 2839f4f41a
commit 40f81d5da6
16 changed files with 639 additions and 1030 deletions
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6
config/fpga/wally-config.vh
View File

@ -93,9 +93,9 @@
`define BOOTROM_BASE 56'h00001000
`define BOOTROM_RANGE 56'h00000FFF
`define UNCORE_RAM_SUPPORTED 1'b0
`define UNCORE_RAM_BASE 56'h100000000
`define UNCORE_RAM_RANGE 56'h07FFFFFF
`define UNCORE_RAM_SUPPORTED 1'b1
`define UNCORE_RAM_BASE 56'h000002000
`define UNCORE_RAM_RANGE 56'h000000FFF
`define EXT_MEM_SUPPORTED 1'b1
`define EXT_MEM_BASE 56'h80000000

445
fpga/constraints/debug2.xdc
View File

@ -717,433 +717,524 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe138]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
# ============== AXI SDC STUFF ================
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe139]
set_property port_width 1 [get_debug_ports u_ila_0/probe139]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
connect_debug_port u_ila_0/probe139 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]]
connect_debug_port u_ila_0/probe139 [get_nets [list {axiSDC/clock_posedge}]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe140]
set_property port_width 32 [get_debug_ports u_ila_0/probe140]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
connect_debug_port u_ila_0/probe140 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]]
connect_debug_port u_ila_0/probe140 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe141]
set_property port_width 25 [get_debug_ports u_ila_0/probe141]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
connect_debug_port u_ila_0/probe141 [get_nets [list {m_axi_awsize[0]} {m_axi_awsize[1]} {m_axi_awsize[2]} ]]
connect_debug_port u_ila_0/probe141 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe142]
set_property port_width 28 [get_debug_ports u_ila_0/probe142]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
connect_debug_port u_ila_0/probe142 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]]
connect_debug_port u_ila_0/probe142 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe143]
set_property port_width 1 [get_debug_ports u_ila_0/probe143]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]]
connect_debug_port u_ila_0/probe143 [get_nets [list {axiSDC/software_reset_reg}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe144]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} {m_axi_awaddr[31]}]]
connect_debug_port u_ila_0/probe144 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe145]
set_property port_width 32 [get_debug_ports u_ila_0/probe145]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
connect_debug_port u_ila_0/probe145 [get_nets [list {m_axi_awprot[0]} {m_axi_awprot[1]} {m_axi_awprot[2]} ]]
connect_debug_port u_ila_0/probe145 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe146]
set_property port_width 32 [get_debug_ports u_ila_0/probe146]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
connect_debug_port u_ila_0/probe146 [get_nets [list {m_axi_awvalid}]]
connect_debug_port u_ila_0/probe146 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe147]
set_property port_width 32 [get_debug_ports u_ila_0/probe147]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
connect_debug_port u_ila_0/probe147 [get_nets [list {m_axi_awready}]]
connect_debug_port u_ila_0/probe147 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe148]
set_property port_width 12 [get_debug_ports u_ila_0/probe148]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
connect_debug_port u_ila_0/probe148 [get_nets [list {m_axi_awlock}]]
connect_debug_port u_ila_0/probe148 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe149]
set_property port_width 2 [get_debug_ports u_ila_0/probe149]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149]
connect_debug_port u_ila_0/probe149 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]]
connect_debug_port u_ila_0/probe149 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe150]
set_property port_width 5 [get_debug_ports u_ila_0/probe150]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150]
connect_debug_port u_ila_0/probe150 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]]
connect_debug_port u_ila_0/probe150 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe151]
set_property port_width 6 [get_debug_ports u_ila_0/probe151]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151]
connect_debug_port u_ila_0/probe151 [get_nets [list {m_axi_wlast}]]
connect_debug_port u_ila_0/probe151 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe152]
set_property port_width 6 [get_debug_ports u_ila_0/probe152]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152]
connect_debug_port u_ila_0/probe152 [get_nets [list {m_axi_wvalid}]]
connect_debug_port u_ila_0/probe152 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe153]
set_property port_width 5 [get_debug_ports u_ila_0/probe153]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153]
connect_debug_port u_ila_0/probe153 [get_nets [list {m_axi_wready}]]
connect_debug_port u_ila_0/probe153 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe154]
set_property port_width 6 [get_debug_ports u_ila_0/probe154]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154]
connect_debug_port u_ila_0/probe154 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]]
connect_debug_port u_ila_0/probe154 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe155]
set_property port_width 16 [get_debug_ports u_ila_0/probe155]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155]
connect_debug_port u_ila_0/probe155 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]]
connect_debug_port u_ila_0/probe155 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe156]
set_property port_width 8 [get_debug_ports u_ila_0/probe156]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156]
connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_bvalid}]]
connect_debug_port u_ila_0/probe156 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe157]
set_property port_width 4 [get_debug_ports u_ila_0/probe157]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157]
connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_bready}]]
connect_debug_port u_ila_0/probe157 [get_nets [list {s00_axi_awid[0]} {s00_axi_awid[1]} {s00_axi_awid[2]} {s00_axi_awid[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe158]
set_property port_width 32 [get_debug_ports u_ila_0/probe158]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158]
connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]]
connect_debug_port u_ila_0/probe158 [get_nets [list {s00_axi_awaddr[0]} {s00_axi_awaddr[1]} {s00_axi_awaddr[2]} {s00_axi_awaddr[3]} {s00_axi_awaddr[4]} {s00_axi_awaddr[5]} {s00_axi_awaddr[6]} {s00_axi_awaddr[7]} {s00_axi_awaddr[8]} {s00_axi_awaddr[9]} {s00_axi_awaddr[10]} {s00_axi_awaddr[11]} {s00_axi_awaddr[12]} {s00_axi_awaddr[13]} {s00_axi_awaddr[14]} {s00_axi_awaddr[15]} {s00_axi_awaddr[16]} {s00_axi_awaddr[17]} {s00_axi_awaddr[18]} {s00_axi_awaddr[19]} {s00_axi_awaddr[20]} {s00_axi_awaddr[21]} {s00_axi_awaddr[22]} {s00_axi_awaddr[23]} {s00_axi_awaddr[24]} {s00_axi_awaddr[25]} {s00_axi_awaddr[26]} {s00_axi_awaddr[27]} {s00_axi_awaddr[28]} {s00_axi_awaddr[29]} {s00_axi_awaddr[30]} {s00_axi_awaddr[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe159]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159]
connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]]
connect_debug_port u_ila_0/probe159 [get_nets [list {s00_axi_awlen[0]} {s00_axi_awlen[1]} {s00_axi_awlen[2]} {s00_axi_awlen[3]} {s00_axi_awlen[4]} {s00_axi_awlen[5]} {s00_axi_awlen[6]} {s00_axi_awlen[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe160]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160]
connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]]
connect_debug_port u_ila_0/probe160 [get_nets [list {s00_axi_awsize[0]} {s00_axi_awsize[1]} {s00_axi_awsize[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe161]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161]
connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]]
connect_debug_port u_ila_0/probe161 [get_nets [list {s00_axi_awburst[0]} {s00_axi_awburst[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe162]
set_property port_width 1 [get_debug_ports u_ila_0/probe162]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162]
connect_debug_port u_ila_0/probe162 [get_nets [list {m_axi_arprot[0]} {m_axi_arprot[1]} {m_axi_arprot[2]} ]]
connect_debug_port u_ila_0/probe162 [get_nets [list {s00_axi_awlock}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe163]
set_property port_width 1 [get_debug_ports u_ila_0/probe163]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163]
connect_debug_port u_ila_0/probe163 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]]
connect_debug_port u_ila_0/probe163 [get_nets [list {s00_axi_awvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe164]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164]
connect_debug_port u_ila_0/probe164 [get_nets [list {m_axi_arvalid}]]
connect_debug_port u_ila_0/probe164 [get_nets [list {s00_axi_awready}]]
create_debug_port u_ila_0 probe
set_property port_width 31 [get_debug_ports u_ila_0/probe165]
set_property port_width 64 [get_debug_ports u_ila_0/probe165]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165]
connect_debug_port u_ila_0/probe165 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} ]]
connect_debug_port u_ila_0/probe165 [get_nets [list {s00_axi_wdata[0]} {s00_axi_wdata[1]} {s00_axi_wdata[2]} {s00_axi_wdata[3]} {s00_axi_wdata[4]} {s00_axi_wdata[5]} {s00_axi_wdata[6]} {s00_axi_wdata[7]} {s00_axi_wdata[8]} {s00_axi_wdata[9]} {s00_axi_wdata[10]} {s00_axi_wdata[11]} {s00_axi_wdata[12]} {s00_axi_wdata[13]} {s00_axi_wdata[14]} {s00_axi_wdata[15]} {s00_axi_wdata[16]} {s00_axi_wdata[17]} {s00_axi_wdata[18]} {s00_axi_wdata[19]} {s00_axi_wdata[20]} {s00_axi_wdata[21]} {s00_axi_wdata[22]} {s00_axi_wdata[23]} {s00_axi_wdata[24]} {s00_axi_wdata[25]} {s00_axi_wdata[26]} {s00_axi_wdata[27]} {s00_axi_wdata[28]} {s00_axi_wdata[29]} {s00_axi_wdata[30]} {s00_axi_wdata[31]} {s00_axi_wdata[32]} {s00_axi_wdata[33]} {s00_axi_wdata[34]} {s00_axi_wdata[35]} {s00_axi_wdata[36]} {s00_axi_wdata[37]} {s00_axi_wdata[38]} {s00_axi_wdata[39]} {s00_axi_wdata[40]} {s00_axi_wdata[41]} {s00_axi_wdata[42]} {s00_axi_wdata[43]} {s00_axi_wdata[44]} {s00_axi_wdata[45]} {s00_axi_wdata[46]} {s00_axi_wdata[47]} {s00_axi_wdata[48]} {s00_axi_wdata[49]} {s00_axi_wdata[50]} {s00_axi_wdata[51]} {s00_axi_wdata[52]} {s00_axi_wdata[53]} {s00_axi_wdata[54]} {s00_axi_wdata[55]} {s00_axi_wdata[56]} {s00_axi_wdata[57]} {s00_axi_wdata[58]} {s00_axi_wdata[59]} {s00_axi_wdata[60]} {s00_axi_wdata[61]} {s00_axi_wdata[62]} {s00_axi_wdata[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe166]
set_property port_width 8 [get_debug_ports u_ila_0/probe166]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166]
connect_debug_port u_ila_0/probe166 [get_nets [list {m_axi_arlock}]]
connect_debug_port u_ila_0/probe166 [get_nets [list {s00_axi_wstrb[0]} {s00_axi_wstrb[1]} {s00_axi_wstrb[2]} {s00_axi_wstrb[3]} {s00_axi_wstrb[4]} {s00_axi_wstrb[5]} {s00_axi_wstrb[6]} {s00_axi_wstrb[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe167]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167]
connect_debug_port u_ila_0/probe167 [get_nets [list {m_axi_arready}]]
connect_debug_port u_ila_0/probe167 [get_nets [list {s00_axi_wlast}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe168]
set_property port_width 1 [get_debug_ports u_ila_0/probe168]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168]
connect_debug_port u_ila_0/probe168 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]]
connect_debug_port u_ila_0/probe168 [get_nets [list {s00_axi_wvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe169]
set_property port_width 1 [get_debug_ports u_ila_0/probe169]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169]
connect_debug_port u_ila_0/probe169 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]]
connect_debug_port u_ila_0/probe169 [get_nets [list {s00_axi_wready}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe170]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170]
connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]]
connect_debug_port u_ila_0/probe170 [get_nets [list {s00_axi_bresp[0]} {s00_axi_bresp[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe171]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171]
connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_rvalid}]]
connect_debug_port u_ila_0/probe171 [get_nets [list {s00_axi_bvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe172]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172]
connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_rlast}]]
connect_debug_port u_ila_0/probe172 [get_nets [list {s00_axi_bready}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe173]
set_property port_width 32 [get_debug_ports u_ila_0/probe173]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173]
connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]]
connect_debug_port u_ila_0/probe173 [get_nets [list {s00_axi_araddr[0]} {s00_axi_araddr[1]} {s00_axi_araddr[2]} {s00_axi_araddr[3]} {s00_axi_araddr[4]} {s00_axi_araddr[5]} {s00_axi_araddr[6]} {s00_axi_araddr[7]} {s00_axi_araddr[8]} {s00_axi_araddr[9]} {s00_axi_araddr[10]} {s00_axi_araddr[11]} {s00_axi_araddr[12]} {s00_axi_araddr[13]} {s00_axi_araddr[14]} {s00_axi_araddr[15]} {s00_axi_araddr[16]} {s00_axi_araddr[17]} {s00_axi_araddr[18]} {s00_axi_araddr[19]} {s00_axi_araddr[20]} {s00_axi_araddr[21]} {s00_axi_araddr[22]} {s00_axi_araddr[23]} {s00_axi_araddr[24]} {s00_axi_araddr[25]} {s00_axi_araddr[26]} {s00_axi_araddr[27]} {s00_axi_araddr[28]} {s00_axi_araddr[29]} {s00_axi_araddr[30]} {s00_axi_araddr[31]} ]]
# ============== AXI SDC STUFF ================
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe174]
set_property port_width 8 [get_debug_ports u_ila_0/probe174]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174]
connect_debug_port u_ila_0/probe174 [get_nets [list {axiSDC/clock_posedge}]]
connect_debug_port u_ila_0/probe174 [get_nets [list {s00_axi_arlen[0]} {s00_axi_arlen[1]} {s00_axi_arlen[2]} {s00_axi_arlen[3]} {s00_axi_arlen[4]} {s00_axi_arlen[5]} {s00_axi_arlen[6]} {s00_axi_arlen[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe175]
set_property port_width 3 [get_debug_ports u_ila_0/probe175]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175]
connect_debug_port u_ila_0/probe175 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]]
connect_debug_port u_ila_0/probe175 [get_nets [list {s00_axi_arsize[0]} {s00_axi_arsize[1]} {s00_axi_arsize[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 25 [get_debug_ports u_ila_0/probe176]
set_property port_width 2 [get_debug_ports u_ila_0/probe176]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176]
connect_debug_port u_ila_0/probe176 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]]
connect_debug_port u_ila_0/probe176 [get_nets [list {s00_axi_arburst[0]} {s00_axi_arburst[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 28 [get_debug_ports u_ila_0/probe177]
set_property port_width 1 [get_debug_ports u_ila_0/probe177]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177]
connect_debug_port u_ila_0/probe177 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]]
connect_debug_port u_ila_0/probe177 [get_nets [list {s00_axi_arvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe178]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178]
connect_debug_port u_ila_0/probe178 [get_nets [list {axiSDC/software_reset_reg}]]
connect_debug_port u_ila_0/probe178 [get_nets [list {s00_axi_arready}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe179]
set_property port_width 64 [get_debug_ports u_ila_0/probe179]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179]
connect_debug_port u_ila_0/probe179 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]]
connect_debug_port u_ila_0/probe179 [get_nets [list {s00_axi_rdata[0]} {s00_axi_rdata[1]} {s00_axi_rdata[2]} {s00_axi_rdata[3]} {s00_axi_rdata[4]} {s00_axi_rdata[5]} {s00_axi_rdata[6]} {s00_axi_rdata[7]} {s00_axi_rdata[8]} {s00_axi_rdata[9]} {s00_axi_rdata[10]} {s00_axi_rdata[11]} {s00_axi_rdata[12]} {s00_axi_rdata[13]} {s00_axi_rdata[14]} {s00_axi_rdata[15]} {s00_axi_rdata[16]} {s00_axi_rdata[17]} {s00_axi_rdata[18]} {s00_axi_rdata[19]} {s00_axi_rdata[20]} {s00_axi_rdata[21]} {s00_axi_rdata[22]} {s00_axi_rdata[23]} {s00_axi_rdata[24]} {s00_axi_rdata[25]} {s00_axi_rdata[26]} {s00_axi_rdata[27]} {s00_axi_rdata[28]} {s00_axi_rdata[29]} {s00_axi_rdata[30]} {s00_axi_rdata[31]} {s00_axi_rdata[32]} {s00_axi_rdata[33]} {s00_axi_rdata[34]} {s00_axi_rdata[35]} {s00_axi_rdata[36]} {s00_axi_rdata[37]} {s00_axi_rdata[38]} {s00_axi_rdata[39]} {s00_axi_rdata[40]} {s00_axi_rdata[41]} {s00_axi_rdata[42]} {s00_axi_rdata[43]} {s00_axi_rdata[44]} {s00_axi_rdata[45]} {s00_axi_rdata[46]} {s00_axi_rdata[47]} {s00_axi_rdata[48]} {s00_axi_rdata[49]} {s00_axi_rdata[50]} {s00_axi_rdata[51]} {s00_axi_rdata[52]} {s00_axi_rdata[53]} {s00_axi_rdata[54]} {s00_axi_rdata[55]} {s00_axi_rdata[56]} {s00_axi_rdata[57]} {s00_axi_rdata[58]} {s00_axi_rdata[59]} {s00_axi_rdata[60]} {s00_axi_rdata[61]} {s00_axi_rdata[62]} {s00_axi_rdata[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe180]
set_property port_width 2 [get_debug_ports u_ila_0/probe180]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180]
connect_debug_port u_ila_0/probe180 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]]
connect_debug_port u_ila_0/probe180 [get_nets [list {s00_axi_rresp[0]} {s00_axi_rresp[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe181]
set_property port_width 1 [get_debug_ports u_ila_0/probe181]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181]
connect_debug_port u_ila_0/probe181 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]]
connect_debug_port u_ila_0/probe181 [get_nets [list {s00_axi_rlast}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe182]
set_property port_width 1 [get_debug_ports u_ila_0/probe182]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182]
connect_debug_port u_ila_0/probe182 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]]
connect_debug_port u_ila_0/probe182 [get_nets [list {s00_axi_rvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe183]
set_property port_width 1 [get_debug_ports u_ila_0/probe183]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183]
connect_debug_port u_ila_0/probe183 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]]
connect_debug_port u_ila_0/probe183 [get_nets [list {s00_axi_rready}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe184]
set_property port_width 4 [get_debug_ports u_ila_0/probe184]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184]
connect_debug_port u_ila_0/probe184 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]]
connect_debug_port u_ila_0/probe184 [get_nets [list {s00_axi_bid[0]} {s00_axi_bid[1]} {s00_axi_bid[2]} {s00_axi_bid[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 5 [get_debug_ports u_ila_0/probe185]
set_property port_width 4 [get_debug_ports u_ila_0/probe185]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185]
connect_debug_port u_ila_0/probe185 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]]
connect_debug_port u_ila_0/probe185 [get_nets [list {s00_axi_rid[0]} {s00_axi_rid[1]} {s00_axi_rid[2]} {s00_axi_rid[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 6 [get_debug_ports u_ila_0/probe186]
set_property port_width 1 [get_debug_ports u_ila_0/probe186]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186]
connect_debug_port u_ila_0/probe186 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]]
connect_debug_port u_ila_0/probe186 [get_nets [list {s00_axi_awlock}]]
create_debug_port u_ila_0 probe
set_property port_width 6 [get_debug_ports u_ila_0/probe187]
set_property port_width 4 [get_debug_ports u_ila_0/probe187]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187]
connect_debug_port u_ila_0/probe187 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]]
connect_debug_port u_ila_0/probe187 [get_nets [list {m01_axi_awid[0]} {m01_axi_awid[1]} {m01_axi_awid[2]} {m01_axi_awid[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 5 [get_debug_ports u_ila_0/probe188]
set_property port_width 32 [get_debug_ports u_ila_0/probe188]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188]
connect_debug_port u_ila_0/probe188 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]]
connect_debug_port u_ila_0/probe188 [get_nets [list {m01_axi_awaddr[0]} {m01_axi_awaddr[1]} {m01_axi_awaddr[2]} {m01_axi_awaddr[3]} {m01_axi_awaddr[4]} {m01_axi_awaddr[5]} {m01_axi_awaddr[6]} {m01_axi_awaddr[7]} {m01_axi_awaddr[8]} {m01_axi_awaddr[9]} {m01_axi_awaddr[10]} {m01_axi_awaddr[11]} {m01_axi_awaddr[12]} {m01_axi_awaddr[13]} {m01_axi_awaddr[14]} {m01_axi_awaddr[15]} {m01_axi_awaddr[16]} {m01_axi_awaddr[17]} {m01_axi_awaddr[18]} {m01_axi_awaddr[19]} {m01_axi_awaddr[20]} {m01_axi_awaddr[21]} {m01_axi_awaddr[22]} {m01_axi_awaddr[23]} {m01_axi_awaddr[24]} {m01_axi_awaddr[25]} {m01_axi_awaddr[26]} {m01_axi_awaddr[27]} {m01_axi_awaddr[28]} {m01_axi_awaddr[29]} {m01_axi_awaddr[30]} {m01_axi_awaddr[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 6 [get_debug_ports u_ila_0/probe189]
set_property port_width 8 [get_debug_ports u_ila_0/probe189]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189]
connect_debug_port u_ila_0/probe189 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]]
connect_debug_port u_ila_0/probe189 [get_nets [list {m01_axi_awlen[0]} {m01_axi_awlen[1]} {m01_axi_awlen[2]} {m01_axi_awlen[3]} {m01_axi_awlen[4]} {m01_axi_awlen[5]} {m01_axi_awlen[6]} {m01_axi_awlen[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe190]
set_property port_width 3 [get_debug_ports u_ila_0/probe190]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190]
connect_debug_port u_ila_0/probe190 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]]
connect_debug_port u_ila_0/probe190 [get_nets [list {m01_axi_awsize[0]} {m01_axi_awsize[1]} {m01_axi_awsize[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe191]
set_property port_width 2 [get_debug_ports u_ila_0/probe191]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191]
connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]]
connect_debug_port u_ila_0/probe191 [get_nets [list {m01_axi_awburst[0]} {m01_axi_awburst[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe192]
set_property port_width 1 [get_debug_ports u_ila_0/probe192]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192]
connect_debug_port u_ila_0/probe192 [get_nets [list {SDCin_axi_awaddr[0]} {SDCin_axi_awaddr[1]} {SDCin_axi_awaddr[2]} {SDCin_axi_awaddr[3]} {SDCin_axi_awaddr[4]} {SDCin_axi_awaddr[5]} {SDCin_axi_awaddr[6]} {SDCin_axi_awaddr[7]} {SDCin_axi_awaddr[8]} {SDCin_axi_awaddr[9]} {SDCin_axi_awaddr[10]} {SDCin_axi_awaddr[11]} {SDCin_axi_awaddr[12]} {SDCin_axi_awaddr[13]} {SDCin_axi_awaddr[14]} {SDCin_axi_awaddr[15]} {SDCin_axi_awaddr[16]} {SDCin_axi_awaddr[17]} {SDCin_axi_awaddr[18]} {SDCin_axi_awaddr[19]} {SDCin_axi_awaddr[20]} {SDCin_axi_awaddr[21]} {SDCin_axi_awaddr[22]} {SDCin_axi_awaddr[23]} {SDCin_axi_awaddr[24]} {SDCin_axi_awaddr[25]} {SDCin_axi_awaddr[26]} {SDCin_axi_awaddr[27]} {SDCin_axi_awaddr[28]} {SDCin_axi_awaddr[29]} {SDCin_axi_awaddr[30]} {SDCin_axi_awaddr[31]} ]]
connect_debug_port u_ila_0/probe192 [get_nets [list {m01_axi_awlock}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe193]
set_property port_width 4 [get_debug_ports u_ila_0/probe193]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193]
connect_debug_port u_ila_0/probe193 [get_nets [list {SDCin_axi_awvalid}]]
connect_debug_port u_ila_0/probe193 [get_nets [list {m01_axi_awcache[0]} {m01_axi_awcache[1]} {m01_axi_awcache[2]} {m01_axi_awcache[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe194]
set_property port_width 3 [get_debug_ports u_ila_0/probe194]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194]
connect_debug_port u_ila_0/probe194 [get_nets [list {SDCin_axi_awready}]]
connect_debug_port u_ila_0/probe194 [get_nets [list {m01_axi_awprot[0]} {m01_axi_awprot[1]} {m01_axi_awprot[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe195]
set_property port_width 4 [get_debug_ports u_ila_0/probe195]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195]
connect_debug_port u_ila_0/probe195 [get_nets [list {SDCin_axi_wdata[0]} {SDCin_axi_wdata[1]} {SDCin_axi_wdata[2]} {SDCin_axi_wdata[3]} {SDCin_axi_wdata[4]} {SDCin_axi_wdata[5]} {SDCin_axi_wdata[6]} {SDCin_axi_wdata[7]} {SDCin_axi_wdata[8]} {SDCin_axi_wdata[9]} {SDCin_axi_wdata[10]} {SDCin_axi_wdata[11]} {SDCin_axi_wdata[12]} {SDCin_axi_wdata[13]} {SDCin_axi_wdata[14]} {SDCin_axi_wdata[15]} {SDCin_axi_wdata[16]} {SDCin_axi_wdata[17]} {SDCin_axi_wdata[18]} {SDCin_axi_wdata[19]} {SDCin_axi_wdata[20]} {SDCin_axi_wdata[21]} {SDCin_axi_wdata[22]} {SDCin_axi_wdata[23]} {SDCin_axi_wdata[24]} {SDCin_axi_wdata[25]} {SDCin_axi_wdata[26]} {SDCin_axi_wdata[27]} {SDCin_axi_wdata[28]} {SDCin_axi_wdata[29]} {SDCin_axi_wdata[30]} {SDCin_axi_wdata[31]} ]]
connect_debug_port u_ila_0/probe195 [get_nets [list {m01_axi_awregion[0]} {m01_axi_awregion[1]} {m01_axi_awregion[2]} {m01_axi_awregion[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe196]
set_property port_width 4 [get_debug_ports u_ila_0/probe196]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196]
connect_debug_port u_ila_0/probe196 [get_nets [list {SDCin_axi_wvalid}]]
connect_debug_port u_ila_0/probe196 [get_nets [list {m01_axi_awqos[0]} {m01_axi_awqos[1]} {m01_axi_awqos[2]} {m01_axi_awqos[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe197]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197]
connect_debug_port u_ila_0/probe197 [get_nets [list {SDCin_axi_wready}]]
connect_debug_port u_ila_0/probe197 [get_nets [list {m01_axi_awvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe198]
set_property port_width 1 [get_debug_ports u_ila_0/probe198]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198]
connect_debug_port u_ila_0/probe198 [get_nets [list {SDCin_axi_bresp[0]} {SDCin_axi_bresp[1]} ]]
connect_debug_port u_ila_0/probe198 [get_nets [list {m01_axi_awready}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe199]
set_property port_width 64 [get_debug_ports u_ila_0/probe199]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199]
connect_debug_port u_ila_0/probe199 [get_nets [list {SDCin_axi_bvalid}]]
connect_debug_port u_ila_0/probe199 [get_nets [list {m01_axi_wdata[0]} {m01_axi_wdata[1]} {m01_axi_wdata[2]} {m01_axi_wdata[3]} {m01_axi_wdata[4]} {m01_axi_wdata[5]} {m01_axi_wdata[6]} {m01_axi_wdata[7]} {m01_axi_wdata[8]} {m01_axi_wdata[9]} {m01_axi_wdata[10]} {m01_axi_wdata[11]} {m01_axi_wdata[12]} {m01_axi_wdata[13]} {m01_axi_wdata[14]} {m01_axi_wdata[15]} {m01_axi_wdata[16]} {m01_axi_wdata[17]} {m01_axi_wdata[18]} {m01_axi_wdata[19]} {m01_axi_wdata[20]} {m01_axi_wdata[21]} {m01_axi_wdata[22]} {m01_axi_wdata[23]} {m01_axi_wdata[24]} {m01_axi_wdata[25]} {m01_axi_wdata[26]} {m01_axi_wdata[27]} {m01_axi_wdata[28]} {m01_axi_wdata[29]} {m01_axi_wdata[30]} {m01_axi_wdata[31]} {m01_axi_wdata[32]} {m01_axi_wdata[33]} {m01_axi_wdata[34]} {m01_axi_wdata[35]} {m01_axi_wdata[36]} {m01_axi_wdata[37]} {m01_axi_wdata[38]} {m01_axi_wdata[39]} {m01_axi_wdata[40]} {m01_axi_wdata[41]} {m01_axi_wdata[42]} {m01_axi_wdata[43]} {m01_axi_wdata[44]} {m01_axi_wdata[45]} {m01_axi_wdata[46]} {m01_axi_wdata[47]} {m01_axi_wdata[48]} {m01_axi_wdata[49]} {m01_axi_wdata[50]} {m01_axi_wdata[51]} {m01_axi_wdata[52]} {m01_axi_wdata[53]} {m01_axi_wdata[54]} {m01_axi_wdata[55]} {m01_axi_wdata[56]} {m01_axi_wdata[57]} {m01_axi_wdata[58]} {m01_axi_wdata[59]} {m01_axi_wdata[60]} {m01_axi_wdata[61]} {m01_axi_wdata[62]} {m01_axi_wdata[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe200]
set_property port_width 4 [get_debug_ports u_ila_0/probe200]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200]
connect_debug_port u_ila_0/probe200 [get_nets [list {SDCin_axi_bready}]]
connect_debug_port u_ila_0/probe200 [get_nets [list {m01_axi_wstrb[0]} {m01_axi_wstrb[1]} {m01_axi_wstrb[2]} {m01_axi_wstrb[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe201]
set_property port_width 1 [get_debug_ports u_ila_0/probe201]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201]
connect_debug_port u_ila_0/probe201 [get_nets [list {SDCin_axi_araddr[0]} {SDCin_axi_araddr[1]} {SDCin_axi_araddr[2]} {SDCin_axi_araddr[3]} {SDCin_axi_araddr[4]} {SDCin_axi_araddr[5]} {SDCin_axi_araddr[6]} {SDCin_axi_araddr[7]} {SDCin_axi_araddr[8]} {SDCin_axi_araddr[9]} {SDCin_axi_araddr[10]} {SDCin_axi_araddr[11]} {SDCin_axi_araddr[12]} {SDCin_axi_araddr[13]} {SDCin_axi_araddr[14]} {SDCin_axi_araddr[15]} {SDCin_axi_araddr[16]} {SDCin_axi_araddr[17]} {SDCin_axi_araddr[18]} {SDCin_axi_araddr[19]} {SDCin_axi_araddr[20]} {SDCin_axi_araddr[21]} {SDCin_axi_araddr[22]} {SDCin_axi_araddr[23]} {SDCin_axi_araddr[24]} {SDCin_axi_araddr[25]} {SDCin_axi_araddr[26]} {SDCin_axi_araddr[27]} {SDCin_axi_araddr[28]} {SDCin_axi_araddr[29]} {SDCin_axi_araddr[30]} {SDCin_axi_araddr[31]} ]]
connect_debug_port u_ila_0/probe201 [get_nets [list {m01_axi_wlast}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe202]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202]
connect_debug_port u_ila_0/probe202 [get_nets [list {SDCin_axi_arvalid}]]
connect_debug_port u_ila_0/probe202 [get_nets [list {m01_axi_wvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe203]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203]
connect_debug_port u_ila_0/probe203 [get_nets [list {SDCin_axi_arready}]]
connect_debug_port u_ila_0/probe203 [get_nets [list {m01_axi_wready}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe204]
set_property port_width 4 [get_debug_ports u_ila_0/probe204]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204]
connect_debug_port u_ila_0/probe204 [get_nets [list {SDCin_axi_rdata[0]} {SDCin_axi_rdata[1]} {SDCin_axi_rdata[2]} {SDCin_axi_rdata[3]} {SDCin_axi_rdata[4]} {SDCin_axi_rdata[5]} {SDCin_axi_rdata[6]} {SDCin_axi_rdata[7]} {SDCin_axi_rdata[8]} {SDCin_axi_rdata[9]} {SDCin_axi_rdata[10]} {SDCin_axi_rdata[11]} {SDCin_axi_rdata[12]} {SDCin_axi_rdata[13]} {SDCin_axi_rdata[14]} {SDCin_axi_rdata[15]} {SDCin_axi_rdata[16]} {SDCin_axi_rdata[17]} {SDCin_axi_rdata[18]} {SDCin_axi_rdata[19]} {SDCin_axi_rdata[20]} {SDCin_axi_rdata[21]} {SDCin_axi_rdata[22]} {SDCin_axi_rdata[23]} {SDCin_axi_rdata[24]} {SDCin_axi_rdata[25]} {SDCin_axi_rdata[26]} {SDCin_axi_rdata[27]} {SDCin_axi_rdata[28]} {SDCin_axi_rdata[29]} {SDCin_axi_rdata[30]} {SDCin_axi_rdata[31]} ]]
connect_debug_port u_ila_0/probe204 [get_nets [list {m01_axi_bid[0]} {m01_axi_bid[1]} {m01_axi_bid[2]} {m01_axi_bid[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe205]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205]
connect_debug_port u_ila_0/probe205 [get_nets [list {SDCin_axi_rresp[0]} {SDCin_axi_rresp[1]} ]]
connect_debug_port u_ila_0/probe205 [get_nets [list {m01_axi_bresp[0]} {m01_axi_bresp[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe206]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206]
connect_debug_port u_ila_0/probe206 [get_nets [list {SDCin_axi_rvalid}]]
connect_debug_port u_ila_0/probe206 [get_nets [list {m01_axi_bvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe207]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207]
connect_debug_port u_ila_0/probe207 [get_nets [list {SDCin_axi_rready}]]
connect_debug_port u_ila_0/probe207 [get_nets [list {m01_axi_bready}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe208]
set_property port_width 4 [get_debug_ports u_ila_0/probe208]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208]
connect_debug_port u_ila_0/probe208 [get_nets [list {s01_axi_awvalid}]]
connect_debug_port u_ila_0/probe208 [get_nets [list {m01_axi_arid[0]} {m01_axi_arid[1]} {m01_axi_arid[2]} {m01_axi_arid[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe209]
set_property port_width 32 [get_debug_ports u_ila_0/probe209]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209]
connect_debug_port u_ila_0/probe209 [get_nets [list {s01_axi_awready}]]
connect_debug_port u_ila_0/probe209 [get_nets [list {m01_axi_araddr[0]} {m01_axi_araddr[1]} {m01_axi_araddr[2]} {m01_axi_araddr[3]} {m01_axi_araddr[4]} {m01_axi_araddr[5]} {m01_axi_araddr[6]} {m01_axi_araddr[7]} {m01_axi_araddr[8]} {m01_axi_araddr[9]} {m01_axi_araddr[10]} {m01_axi_araddr[11]} {m01_axi_araddr[12]} {m01_axi_araddr[13]} {m01_axi_araddr[14]} {m01_axi_araddr[15]} {m01_axi_araddr[16]} {m01_axi_araddr[17]} {m01_axi_araddr[18]} {m01_axi_araddr[19]} {m01_axi_araddr[20]} {m01_axi_araddr[21]} {m01_axi_araddr[22]} {m01_axi_araddr[23]} {m01_axi_araddr[24]} {m01_axi_araddr[25]} {m01_axi_araddr[26]} {m01_axi_araddr[27]} {m01_axi_araddr[28]} {m01_axi_araddr[29]} {m01_axi_araddr[30]} {m01_axi_araddr[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe210]
set_property port_width 8 [get_debug_ports u_ila_0/probe210]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210]
connect_debug_port u_ila_0/probe210 [get_nets [list {s00_axi_awvalid}]]
connect_debug_port u_ila_0/probe210 [get_nets [list {m01_axi_arlen[0]} {m01_axi_arlen[1]} {m01_axi_arlen[2]} {m01_axi_arlen[3]} {m01_axi_arlen[4]} {m01_axi_arlen[5]} {m01_axi_arlen[6]} {m01_axi_arlen[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe211]
set_property port_width 3 [get_debug_ports u_ila_0/probe211]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211]
connect_debug_port u_ila_0/probe211 [get_nets [list {s00_axi_awready}]]
connect_debug_port u_ila_0/probe211 [get_nets [list {m01_axi_arsize[0]} {m01_axi_arsize[1]} {m01_axi_arsize[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe212]
set_property port_width 2 [get_debug_ports u_ila_0/probe212]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212]
connect_debug_port u_ila_0/probe212 [get_nets [list {axi4in_axi_awvalid}]]
connect_debug_port u_ila_0/probe212 [get_nets [list {m01_axi_arburst[0]} {m01_axi_arburst[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe213]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213]
connect_debug_port u_ila_0/probe213 [get_nets [list {axi4in_axi_awready}]]
connect_debug_port u_ila_0/probe213 [get_nets [list {m01_axi_arlock}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe214]
set_property port_width 4 [get_debug_ports u_ila_0/probe214]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214]
connect_debug_port u_ila_0/probe214 [get_nets [list {SDCout_axi_awvalid}]]
connect_debug_port u_ila_0/probe214 [get_nets [list {m01_axi_arcache[0]} {m01_axi_arcache[1]} {m01_axi_arcache[2]} {m01_axi_arcache[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe215]
set_property port_width 3 [get_debug_ports u_ila_0/probe215]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215]
connect_debug_port u_ila_0/probe215 [get_nets [list {SDCout_axi_awready}]]
connect_debug_port u_ila_0/probe215 [get_nets [list {m01_axi_arprot[0]} {m01_axi_arprot[1]} {m01_axi_arprot[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe216]
set_property port_width 4 [get_debug_ports u_ila_0/probe216]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216]
connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_awvalid}]]
connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_arregion[0]} {m01_axi_arregion[1]} {m01_axi_arregion[2]} {m01_axi_arregion[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe217]
set_property port_width 4 [get_debug_ports u_ila_0/probe217]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217]
connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_awready}]]
connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_arqos[0]} {m01_axi_arqos[1]} {m01_axi_arqos[2]} {m01_axi_arqos[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe218]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe218]
connect_debug_port u_ila_0/probe218 [get_nets [list {m01_axi_arvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe219]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe219]
connect_debug_port u_ila_0/probe219 [get_nets [list {m01_axi_arready}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe220]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe220]
connect_debug_port u_ila_0/probe220 [get_nets [list {m01_axi_rid[0]} {m01_axi_rid[1]} {m01_axi_rid[2]} {m01_axi_rid[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe221]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221]
connect_debug_port u_ila_0/probe221 [get_nets [list {m01_axi_rdata[0]} {m01_axi_rdata[1]} {m01_axi_rdata[2]} {m01_axi_rdata[3]} {m01_axi_rdata[4]} {m01_axi_rdata[5]} {m01_axi_rdata[6]} {m01_axi_rdata[7]} {m01_axi_rdata[8]} {m01_axi_rdata[9]} {m01_axi_rdata[10]} {m01_axi_rdata[11]} {m01_axi_rdata[12]} {m01_axi_rdata[13]} {m01_axi_rdata[14]} {m01_axi_rdata[15]} {m01_axi_rdata[16]} {m01_axi_rdata[17]} {m01_axi_rdata[18]} {m01_axi_rdata[19]} {m01_axi_rdata[20]} {m01_axi_rdata[21]} {m01_axi_rdata[22]} {m01_axi_rdata[23]} {m01_axi_rdata[24]} {m01_axi_rdata[25]} {m01_axi_rdata[26]} {m01_axi_rdata[27]} {m01_axi_rdata[28]} {m01_axi_rdata[29]} {m01_axi_rdata[30]} {m01_axi_rdata[31]} {m01_axi_rdata[32]} {m01_axi_rdata[33]} {m01_axi_rdata[34]} {m01_axi_rdata[35]} {m01_axi_rdata[36]} {m01_axi_rdata[37]} {m01_axi_rdata[38]} {m01_axi_rdata[39]} {m01_axi_rdata[40]} {m01_axi_rdata[41]} {m01_axi_rdata[42]} {m01_axi_rdata[43]} {m01_axi_rdata[44]} {m01_axi_rdata[45]} {m01_axi_rdata[46]} {m01_axi_rdata[47]} {m01_axi_rdata[48]} {m01_axi_rdata[49]} {m01_axi_rdata[50]} {m01_axi_rdata[51]} {m01_axi_rdata[52]} {m01_axi_rdata[53]} {m01_axi_rdata[54]} {m01_axi_rdata[55]} {m01_axi_rdata[56]} {m01_axi_rdata[57]} {m01_axi_rdata[58]} {m01_axi_rdata[59]} {m01_axi_rdata[60]} {m01_axi_rdata[61]} {m01_axi_rdata[62]} {m01_axi_rdata[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe222]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222]
connect_debug_port u_ila_0/probe222 [get_nets [list {m01_axi_rresp[0]} {m01_axi_rresp[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe223]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223]
connect_debug_port u_ila_0/probe223 [get_nets [list {m01_axi_rlast}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe224]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe224]
connect_debug_port u_ila_0/probe224 [get_nets [list {m01_axi_rvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe225]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe225]
connect_debug_port u_ila_0/probe225 [get_nets [list {m01_axi_rready}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe226]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe226]
connect_debug_port u_ila_0/probe226 [get_nets [list {SDCout_axi_awaddr[0]} {SDCout_axi_awaddr[1]} {SDCout_axi_awaddr[2]} {SDCout_axi_awaddr[3]} {SDCout_axi_awaddr[4]} {SDCout_axi_awaddr[5]} {SDCout_axi_awaddr[6]} {SDCout_axi_awaddr[7]} {SDCout_axi_awaddr[8]} {SDCout_axi_awaddr[9]} {SDCout_axi_awaddr[10]} {SDCout_axi_awaddr[11]} {SDCout_axi_awaddr[12]} {SDCout_axi_awaddr[13]} {SDCout_axi_awaddr[14]} {SDCout_axi_awaddr[15]} {SDCout_axi_awaddr[16]} {SDCout_axi_awaddr[17]} {SDCout_axi_awaddr[18]} {SDCout_axi_awaddr[19]} {SDCout_axi_awaddr[20]} {SDCout_axi_awaddr[21]} {SDCout_axi_awaddr[22]} {SDCout_axi_awaddr[23]} {SDCout_axi_awaddr[24]} {SDCout_axi_awaddr[25]} {SDCout_axi_awaddr[26]} {SDCout_axi_awaddr[27]} {SDCout_axi_awaddr[28]} {SDCout_axi_awaddr[29]} {SDCout_axi_awaddr[30]} {SDCout_axi_awaddr[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe227]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe227]
connect_debug_port u_ila_0/probe227 [get_nets [list {SDCout_axi_awlen[0]} {SDCout_axi_awlen[1]} {SDCout_axi_awlen[2]} {SDCout_axi_awlen[3]} {SDCout_axi_awlen[4]} {SDCout_axi_awlen[5]} {SDCout_axi_awlen[6]} {SDCout_axi_awlen[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe228]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe228]
connect_debug_port u_ila_0/probe228 [get_nets [list {SDCout_axi_awvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe229]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe229]
connect_debug_port u_ila_0/probe229 [get_nets [list {SDCout_axi_awready}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe230]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe230]
connect_debug_port u_ila_0/probe230 [get_nets [list {SDCout_axi_wdata[0]} {SDCout_axi_wdata[1]} {SDCout_axi_wdata[2]} {SDCout_axi_wdata[3]} {SDCout_axi_wdata[4]} {SDCout_axi_wdata[5]} {SDCout_axi_wdata[6]} {SDCout_axi_wdata[7]} {SDCout_axi_wdata[8]} {SDCout_axi_wdata[9]} {SDCout_axi_wdata[10]} {SDCout_axi_wdata[11]} {SDCout_axi_wdata[12]} {SDCout_axi_wdata[13]} {SDCout_axi_wdata[14]} {SDCout_axi_wdata[15]} {SDCout_axi_wdata[16]} {SDCout_axi_wdata[17]} {SDCout_axi_wdata[18]} {SDCout_axi_wdata[19]} {SDCout_axi_wdata[20]} {SDCout_axi_wdata[21]} {SDCout_axi_wdata[22]} {SDCout_axi_wdata[23]} {SDCout_axi_wdata[24]} {SDCout_axi_wdata[25]} {SDCout_axi_wdata[26]} {SDCout_axi_wdata[27]} {SDCout_axi_wdata[28]} {SDCout_axi_wdata[29]} {SDCout_axi_wdata[30]} {SDCout_axi_wdata[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe231]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe231]
connect_debug_port u_ila_0/probe231 [get_nets [list {SDCout_axi_wlast}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe232]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe232]
connect_debug_port u_ila_0/probe232 [get_nets [list {SDCout_axi_wvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe233]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe233]
connect_debug_port u_ila_0/probe233 [get_nets [list {SDCout_axi_wready}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe234]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe234]
connect_debug_port u_ila_0/probe234 [get_nets [list {SDCout_axi_bresp[0]} {SDCout_axi_bresp[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe235]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe235]
connect_debug_port u_ila_0/probe235 [get_nets [list {SDCout_axi_bvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe236]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe236]
connect_debug_port u_ila_0/probe236 [get_nets [list {SDCout_axi_bready}]]
create_debug_port u_ila_0 probe
set_property port_width 28 [get_debug_ports u_ila_0/probe237]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe237]
connect_debug_port u_ila_0/probe237 [get_nets [list {axiSDC/sd_data_master0/watchdog[0]} {axiSDC/sd_data_master0/watchdog[1]} {axiSDC/sd_data_master0/watchdog[2]} {axiSDC/sd_data_master0/watchdog[3]} {axiSDC/sd_data_master0/watchdog[4]} {axiSDC/sd_data_master0/watchdog[5]} {axiSDC/sd_data_master0/watchdog[6]} {axiSDC/sd_data_master0/watchdog[7]} {axiSDC/sd_data_master0/watchdog[8]} {axiSDC/sd_data_master0/watchdog[9]} {axiSDC/sd_data_master0/watchdog[10]} {axiSDC/sd_data_master0/watchdog[11]} {axiSDC/sd_data_master0/watchdog[12]} {axiSDC/sd_data_master0/watchdog[13]} {axiSDC/sd_data_master0/watchdog[14]} {axiSDC/sd_data_master0/watchdog[15]} {axiSDC/sd_data_master0/watchdog[16]} {axiSDC/sd_data_master0/watchdog[17]} {axiSDC/sd_data_master0/watchdog[18]} {axiSDC/sd_data_master0/watchdog[19]} {axiSDC/sd_data_master0/watchdog[20]} {axiSDC/sd_data_master0/watchdog[21]} {axiSDC/sd_data_master0/watchdog[22]} {axiSDC/sd_data_master0/watchdog[23]} {axiSDC/sd_data_master0/watchdog[24]} {axiSDC/sd_data_master0/watchdog[25]} {axiSDC/sd_data_master0/watchdog[26]} {axiSDC/sd_data_master0/watchdog[27]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe238]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe238]
connect_debug_port u_ila_0/probe238 [get_nets [list {axiSDC/data_busy}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe239]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe239]
connect_debug_port u_ila_0/probe239 [get_nets [list {axiSDC/sd_data_master0/en_tx_fifo}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe240]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe240]
connect_debug_port u_ila_0/probe240 [get_nets [list {axiSDC/sd_data_master0/fifo_empty}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe241]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe241]
connect_debug_port u_ila_0/probe241 [get_nets [list {axiSDC/sd_data_master0/bus_cycle}]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe242]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe242]
connect_debug_port u_ila_0/probe242 [get_nets [list {axiSDC/sd_data_serial_host0/blkcnt_reg[0]} {axiSDC/sd_data_serial_host0/blkcnt_reg[1]} {axiSDC/sd_data_serial_host0/blkcnt_reg[2]} {axiSDC/sd_data_serial_host0/blkcnt_reg[3]} {axiSDC/sd_data_serial_host0/blkcnt_reg[4]} {axiSDC/sd_data_serial_host0/blkcnt_reg[5]} {axiSDC/sd_data_serial_host0/blkcnt_reg[6]} {axiSDC/sd_data_serial_host0/blkcnt_reg[7]} {axiSDC/sd_data_serial_host0/blkcnt_reg[8]} {axiSDC/sd_data_serial_host0/blkcnt_reg[9]} {axiSDC/sd_data_serial_host0/blkcnt_reg[10]} {axiSDC/sd_data_serial_host0/blkcnt_reg[11]}]]

1
fpga/constraints/marked_debug.txt
View File

@ -101,6 +101,7 @@ uncore/uartPC16550D.sv: logic RXerr
uncore/uartPC16550D.sv: logic THRE
uncore/uartPC16550D.sv: logic rxdataavailintr
uncore/uartPC16550D.sv: logic intrID
uncore/uncore.sv: logic HSELEXTSDCD
uncore/plic_apb.sv: logic MExtInt
uncore/plic_apb.sv: logic Din
uncore/plic_apb.sv: logic requests

4
fpga/generator/xlnx_axi_crossbar.tcl
View File

@ -19,8 +19,8 @@ create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module
set_property -dict [list CONFIG.NUM_SI {2} \
CONFIG.DATA_WIDTH {64} \
CONFIG.ID_WIDTH {4} \
# CONFIG.M01_S01_READ_CONNECTIVITY {0} \
# CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \
CONFIG.M01_S01_READ_CONNECTIVITY {0} \
CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \
CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \
CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \
CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName]

260
fpga/src/fpgaTop.v
View File

@ -74,9 +74,10 @@ module fpgaTop
wire HCLKOpen;
wire HRESETnOpen;
wire [`AHBW-1:0] HRDATAEXT;
wire HREADYEXT;
(* mark_debug = "true" *)wire HREADYEXT;
wire HRESPEXT;
wire HSELEXT;
(* mark_debug = "true" *) wire HSELEXT;
(* mark_debug = "true" *) wire HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB
wire [31:0] HADDR;
wire [`AHBW-1:0] HWDATA;
wire HWRITE;
@ -96,41 +97,41 @@ module fpgaTop
// wire SDCCmdOE;
// wire SDCCmdOut;
(* mark_debug = "true" *) wire [3:0] m_axi_awid;
(* mark_debug = "true" *) wire [7:0] m_axi_awlen;
(* mark_debug = "true" *) wire [2:0] m_axi_awsize;
(* mark_debug = "true" *) wire [1:0] m_axi_awburst;
(* mark_debug = "true" *) wire [3:0] m_axi_awcache;
(* mark_debug = "true" *) wire [31:0] m_axi_awaddr;
(* mark_debug = "true" *) wire [2:0] m_axi_awprot;
(* mark_debug = "true" *) wire m_axi_awvalid;
(* mark_debug = "true" *) wire m_axi_awready;
(* mark_debug = "true" *) wire m_axi_awlock;
(* mark_debug = "true" *) wire [63:0] m_axi_wdata;
(* mark_debug = "true" *) wire [7:0] m_axi_wstrb;
(* mark_debug = "true" *) wire m_axi_wlast;
(* mark_debug = "true" *) wire m_axi_wvalid;
(* mark_debug = "true" *) wire m_axi_wready;
(* mark_debug = "true" *) wire [3:0] m_axi_bid;
(* mark_debug = "true" *) wire [1:0] m_axi_bresp;
(* mark_debug = "true" *) wire m_axi_bvalid;
(* mark_debug = "true" *) wire m_axi_bready;
(* mark_debug = "true" *) wire [3:0] m_axi_arid;
(* mark_debug = "true" *) wire [7:0] m_axi_arlen;
(* mark_debug = "true" *) wire [2:0] m_axi_arsize;
(* mark_debug = "true" *) wire [1:0] m_axi_arburst;
(* mark_debug = "true" *) wire [2:0] m_axi_arprot;
(* mark_debug = "true" *) wire [3:0] m_axi_arcache;
(* mark_debug = "true" *) wire m_axi_arvalid;
(* mark_debug = "true" *) wire [31:0] m_axi_araddr;
(* mark_debug = "true" *) wire m_axi_arlock;
(* mark_debug = "true" *) wire m_axi_arready;
(* mark_debug = "true" *) wire [3:0] m_axi_rid;
(* mark_debug = "true" *) wire [63:0] m_axi_rdata;
(* mark_debug = "true" *) wire [1:0] m_axi_rresp;
(* mark_debug = "true" *) wire m_axi_rvalid;
(* mark_debug = "true" *) wire m_axi_rlast;
(* mark_debug = "true" *) wire m_axi_rready;
wire [3:0] m_axi_awid;
wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst;
wire [3:0] m_axi_awcache;
wire [31:0] m_axi_awaddr;
wire [2:0] m_axi_awprot;
wire m_axi_awvalid;
wire m_axi_awready;
wire m_axi_awlock;
wire [63:0] m_axi_wdata;
wire [7:0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
wire m_axi_wready;
wire [3:0] m_axi_bid;
wire [1:0] m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_bready;
wire [3:0] m_axi_arid;
wire [7:0] m_axi_arlen;
wire [2:0] m_axi_arsize;
wire [1:0] m_axi_arburst;
wire [2:0] m_axi_arprot;
wire [3:0] m_axi_arcache;
wire m_axi_arvalid;
wire [31:0] m_axi_araddr;
wire m_axi_arlock;
wire m_axi_arready;
wire [3:0] m_axi_rid;
wire [63:0] m_axi_rdata;
wire [1:0] m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_rlast;
wire m_axi_rready;
// Extra Bus signals
wire [3:0] BUS_axi_arregion;
@ -187,47 +188,47 @@ module fpgaTop
// Crossbar to Bus ------------------------------------------------
wire s00_axi_aclk;
wire s00_axi_aresetn;
wire [3:0] s00_axi_awid;
wire [31:0]s00_axi_awaddr;
wire [7:0]s00_axi_awlen;
wire [2:0]s00_axi_awsize;
wire [1:0]s00_axi_awburst;
wire [0:0]s00_axi_awlock;
wire [3:0]s00_axi_awcache;
wire [2:0]s00_axi_awprot;
wire [3:0]s00_axi_awregion;
wire [3:0]s00_axi_awqos;
(* mark_debug = "true" *)wire s00_axi_aclk;
(* mark_debug = "true" *)wire s00_axi_aresetn;
(* mark_debug = "true" *)wire [3:0] s00_axi_awid;
(* mark_debug = "true" *)wire [31:0]s00_axi_awaddr;
(* mark_debug = "true" *)wire [7:0]s00_axi_awlen;
(* mark_debug = "true" *)wire [2:0]s00_axi_awsize;
(* mark_debug = "true" *)wire [1:0]s00_axi_awburst;
(* mark_debug = "true" *)wire [0:0]s00_axi_awlock;
(* mark_debug = "true" *)wire [3:0]s00_axi_awcache;
(* mark_debug = "true" *)wire [2:0]s00_axi_awprot;
(* mark_debug = "true" *)wire [3:0]s00_axi_awregion;
(* mark_debug = "true" *)wire [3:0]s00_axi_awqos;
(* mark_debug = "true" *) wire s00_axi_awvalid;
(* mark_debug = "true" *) wire s00_axi_awready;
wire [63:0]s00_axi_wdata;
wire [7:0]s00_axi_wstrb;
wire s00_axi_wlast;
wire s00_axi_wvalid;
wire s00_axi_wready;
wire [1:0]s00_axi_bresp;
wire s00_axi_bvalid;
wire s00_axi_bready;
wire [31:0]s00_axi_araddr;
wire [7:0]s00_axi_arlen;
wire [2:0]s00_axi_arsize;
wire [1:0]s00_axi_arburst;
wire [0:0]s00_axi_arlock;
wire [3:0]s00_axi_arcache;
wire [2:0]s00_axi_arprot;
wire [3:0]s00_axi_arregion;
wire [3:0]s00_axi_arqos;
wire s00_axi_arvalid;
wire s00_axi_arready;
wire [63:0]s00_axi_rdata;
wire [1:0]s00_axi_rresp;
wire s00_axi_rlast;
wire s00_axi_rvalid;
wire s00_axi_rready;
(* mark_debug = "true" *)wire [63:0]s00_axi_wdata;
(* mark_debug = "true" *)wire [7:0]s00_axi_wstrb;
(* mark_debug = "true" *)wire s00_axi_wlast;
(* mark_debug = "true" *)wire s00_axi_wvalid;
(* mark_debug = "true" *)wire s00_axi_wready;
(* mark_debug = "true" *)wire [1:0]s00_axi_bresp;
(* mark_debug = "true" *)wire s00_axi_bvalid;
(* mark_debug = "true" *)wire s00_axi_bready;
(* mark_debug = "true" *)wire [31:0]s00_axi_araddr;
(* mark_debug = "true" *)wire [7:0]s00_axi_arlen;
(* mark_debug = "true" *)wire [2:0]s00_axi_arsize;
(* mark_debug = "true" *)wire [1:0]s00_axi_arburst;
(* mark_debug = "true" *)wire [0:0]s00_axi_arlock;
(* mark_debug = "true" *)wire [3:0]s00_axi_arcache;
(* mark_debug = "true" *)wire [2:0]s00_axi_arprot;
(* mark_debug = "true" *)wire [3:0]s00_axi_arregion;
(* mark_debug = "true" *)wire [3:0]s00_axi_arqos;
(* mark_debug = "true" *)wire s00_axi_arvalid;
(* mark_debug = "true" *)wire s00_axi_arready;
(* mark_debug = "true" *)wire [63:0]s00_axi_rdata;
(* mark_debug = "true" *)wire [1:0]s00_axi_rresp;
(* mark_debug = "true" *)wire s00_axi_rlast;
(* mark_debug = "true" *)wire s00_axi_rvalid;
(* mark_debug = "true" *)wire s00_axi_rready;
wire [3:0] s00_axi_bid;
wire [3:0] s00_axi_rid;
(* mark_debug = "true" *)wire [3:0] s00_axi_bid;
(* mark_debug = "true" *)wire [3:0] s00_axi_rid;
// 64to32 dwidth converter input interface-------------------------
wire s01_axi_aclk;
@ -329,8 +330,8 @@ module fpgaTop
// ----------------------------------------------------------------
// 32to64 dwidth converter input interface -----------------------
wire [31:0]SDCout_axi_awaddr;
wire [7:0]SDCout_axi_awlen;
(* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr;
(* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen;
wire [2:0]SDCout_axi_awsize;
wire [1:0]SDCout_axi_awburst;
wire [0:0]SDCout_axi_awlock;
@ -340,14 +341,14 @@ module fpgaTop
wire [3:0]SDCout_axi_awqos;
(* mark_debug = "true" *) wire SDCout_axi_awvalid;
(* mark_debug = "true" *) wire SDCout_axi_awready;
wire [31:0]SDCout_axi_wdata;
(* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata;
wire [3:0]SDCout_axi_wstrb;
wire SDCout_axi_wlast;
wire SDCout_axi_wvalid;
wire SDCout_axi_wready;
wire [1:0]SDCout_axi_bresp;
wire SDCout_axi_bvalid;
wire SDCout_axi_bready;
(* mark_debug = "true" *) wire SDCout_axi_wlast;
(* mark_debug = "true" *) wire SDCout_axi_wvalid;
(* mark_debug = "true" *)wire SDCout_axi_wready;
(* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp;
(* mark_debug = "true" *) wire SDCout_axi_bvalid;
(* mark_debug = "true" *) wire SDCout_axi_bready;
wire [31:0]SDCout_axi_araddr;
wire [7:0]SDCout_axi_arlen;
wire [2:0]SDCout_axi_arsize;
@ -366,45 +367,45 @@ module fpgaTop
wire SDCout_axi_rready;
// Output Interface
wire [3:0]m01_axi_awid;
wire [31:0]m01_axi_awaddr;
wire [7:0]m01_axi_awlen;
wire [2:0]m01_axi_awsize;
wire [1:0]m01_axi_awburst;
wire [0:0]m01_axi_awlock;
wire [3:0]m01_axi_awcache;
wire [2:0]m01_axi_awprot;
wire [3:0]m01_axi_awregion;
wire [3:0]m01_axi_awqos;
(* mark_debug = "true" *) wire [3:0]m01_axi_awid;
(* mark_debug = "true" *) wire [31:0]m01_axi_awaddr;
(* mark_debug = "true" *) wire [7:0]m01_axi_awlen;
(* mark_debug = "true" *) wire [2:0]m01_axi_awsize;
(* mark_debug = "true" *) wire [1:0]m01_axi_awburst;
(* mark_debug = "true" *) wire [0:0]m01_axi_awlock;
(* mark_debug = "true" *) wire [3:0]m01_axi_awcache;
(* mark_debug = "true" *) wire [2:0]m01_axi_awprot;
(* mark_debug = "true" *) wire [3:0]m01_axi_awregion;
(* mark_debug = "true" *) wire [3:0]m01_axi_awqos;
(* mark_debug = "true" *) wire m01_axi_awvalid;
(* mark_debug = "true" *) wire m01_axi_awready;
wire [63:0]m01_axi_wdata;
wire [3:0]m01_axi_wstrb;
wire m01_axi_wlast;
wire m01_axi_wvalid;
wire m01_axi_wready;
wire [3:0] m01_axi_bid;
wire [1:0]m01_axi_bresp;
wire m01_axi_bvalid;
wire m01_axi_bready;
wire [3:0] m01_axi_arid;
wire [31:0]m01_axi_araddr;
wire [7:0]m01_axi_arlen;
wire [2:0]m01_axi_arsize;
wire [1:0]m01_axi_arburst;
wire [0:0]m01_axi_arlock;
wire [3:0]m01_axi_arcache;
wire [2:0]m01_axi_arprot;
wire [3:0]m01_axi_arregion;
wire [3:0]m01_axi_arqos;
wire m01_axi_arvalid;
wire m01_axi_arready;
wire [3:0] m01_axi_rid;
wire [63:0]m01_axi_rdata;
wire [1:0]m01_axi_rresp;
wire m01_axi_rlast;
wire m01_axi_rvalid;
wire m01_axi_rready;
(* mark_debug = "true" *) wire [63:0]m01_axi_wdata;
(* mark_debug = "true" *) wire [7:0]m01_axi_wstrb;
(* mark_debug = "true" *) wire m01_axi_wlast;
(* mark_debug = "true" *) wire m01_axi_wvalid;
(* mark_debug = "true" *) wire m01_axi_wready;
(* mark_debug = "true" *) wire [3:0] m01_axi_bid;
(* mark_debug = "true" *) wire [1:0]m01_axi_bresp;
(* mark_debug = "true" *) wire m01_axi_bvalid;
(* mark_debug = "true" *) wire m01_axi_bready;
(* mark_debug = "true" *) wire [3:0] m01_axi_arid;
(* mark_debug = "true" *) wire [31:0]m01_axi_araddr;
(* mark_debug = "true" *) wire [7:0]m01_axi_arlen;
(* mark_debug = "true" *) wire [2:0]m01_axi_arsize;
(* mark_debug = "true" *) wire [1:0]m01_axi_arburst;
(* mark_debug = "true" *) wire [0:0]m01_axi_arlock;
(* mark_debug = "true" *) wire [3:0]m01_axi_arcache;
(* mark_debug = "true" *) wire [2:0]m01_axi_arprot;
(* mark_debug = "true" *) wire [3:0]m01_axi_arregion;
(* mark_debug = "true" *) wire [3:0]m01_axi_arqos;
(* mark_debug = "true" *) wire m01_axi_arvalid;
(* mark_debug = "true" *) wire m01_axi_arready;
(* mark_debug = "true" *) wire [3:0] m01_axi_rid;
(* mark_debug = "true" *) wire [63:0]m01_axi_rdata;
(* mark_debug = "true" *) wire [1:0]m01_axi_rresp;
(* mark_debug = "true" *) wire m01_axi_rlast;
(* mark_debug = "true" *) wire m01_axi_rvalid;
(* mark_debug = "true" *) wire m01_axi_rready;
// Old SDC input
// wire [3:0] SDCDatIn;
@ -487,6 +488,7 @@ module fpgaTop
.HREADYEXT(HREADYEXT),
.HRESPEXT(HRESPEXT),
.HSELEXT(HSELEXT),
.HSELEXTSDC(HSELEXTSDC),
.HCLK(HCLKOpen), // open
.HRESETn(HRESETnOpen), // open
.HADDR(HADDR),
@ -517,7 +519,7 @@ module fpgaTop
xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
(.s_ahb_hclk(CPUCLK),
.s_ahb_hresetn(peripheral_aresetn),
.s_ahb_hsel(HSELEXT),
.s_ahb_hsel(HSELEXT | HSELEXTSDC),
.s_ahb_haddr(HADDR),
.s_ahb_hprot(HPROT),
.s_ahb_htrans(HTRANS),
@ -809,7 +811,7 @@ module fpgaTop
.async_resetn(peripheral_aresetn),
// Slave Interface
.s_axi_awaddr(SDCin_axi_awaddr[15:0]),
.s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}),
.s_axi_awvalid(SDCin_axi_awvalid),
.s_axi_awready(SDCin_axi_awready),
.s_axi_wdata(SDCin_axi_wdata),
@ -818,7 +820,7 @@ module fpgaTop
.s_axi_bresp(SDCin_axi_bresp),
.s_axi_bvalid(SDCin_axi_bvalid),
.s_axi_bready(SDCin_axi_bready),
.s_axi_araddr(SDCin_axi_araddr[15:0]),
.s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}),
.s_axi_arvalid(SDCin_axi_arvalid),
.s_axi_arready(SDCin_axi_arready),
.s_axi_rdata(SDCin_axi_rdata),
@ -872,8 +874,8 @@ module fpgaTop
// Slave interface
.s_axi_awaddr(SDCout_axi_awaddr),
.s_axi_awlen(SDCout_axi_awlen),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awsize(3'b010),
.s_axi_awburst(2'b01),
.s_axi_awlock(1'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
@ -882,7 +884,7 @@ module fpgaTop
.s_axi_awvalid(SDCout_axi_awvalid),
.s_axi_awready(SDCout_axi_awready),
.s_axi_wdata(SDCout_axi_wdata),
.s_axi_wstrb(8'b0),
.s_axi_wstrb(8'b11111111),
.s_axi_wlast(SDCout_axi_wlast),
.s_axi_wvalid(SDCout_axi_wvalid),
.s_axi_wready(SDCout_axi_wready),
@ -891,8 +893,8 @@ module fpgaTop
.s_axi_bready(SDCout_axi_bready),
.s_axi_araddr(SDCout_axi_araddr),
.s_axi_arlen(SDCout_axi_arlen),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arsize(3'b010),
.s_axi_arburst(2'b01),
.s_axi_arlock(1'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),

2
pipelined/src/uncore/newsdc/axi_sdc_controller.v
View File

@ -162,7 +162,7 @@ wire [31:0] data_in_rx_fifo;
wire en_tx_fifo;
wire en_rx_fifo;
wire sd_data_busy;
wire data_busy;
(* mark_debug = "true" *) wire data_busy;
wire data_crc_ok;
wire tx_fifo_re;
wire rx_fifo_we;

8
pipelined/src/uncore/newsdc/sd_data_master.v
View File

@ -42,12 +42,12 @@ module sd_data_master (
output reg d_write,
output reg d_read,
// To fifo filler
output reg en_tx_fifo,
(* mark_debug = "true" *) output reg en_tx_fifo,
output reg en_rx_fifo,
input fifo_empty,
(* mark_debug = "true" *) input fifo_empty,
input fifo_ready,
input fifo_full,
input bus_cycle,
(* mark_debug = "true" *) input bus_cycle,
// SD-DATA_Host
input xfr_complete,
input crc_error,
@ -63,7 +63,7 @@ localparam START_TX_FIFO = 4'b0010;
localparam START_RX_FIFO = 4'b0100;
localparam DATA_TRANSFER = 4'b1000;
reg [`DATA_TIMEOUT_W-1:0] watchdog;
(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
always @(posedge clock) begin

2
pipelined/src/uncore/newsdc/sd_data_serial_host.v
View File

@ -66,7 +66,7 @@ reg [`BLKSIZE_W+4-1:0] data_cycles;
reg [`BLKSIZE_W+4-1:0] transf_cnt;
reg [3:0] drt_bit;
reg [3:0] drt_reg;
reg [`BLKCNT_W-1:0] blkcnt_reg;
(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] blkcnt_reg;
reg [1:0] byte_alignment_reg;
reg [3:0] crc_bit;
reg [3:0] last_din;

8
src/generic/mem/ram1p1rwbe.sv
View File

@ -34,7 +34,7 @@
`include "wally-config.vh"
module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256, PRELOAD_ENABLED=0) (
input logic clk,
input logic ce,
input logic [$clog2(DEPTH)-1:0] addr,
@ -95,6 +95,12 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
end else begin: ram
integer i;
if (PRELOAD_ENABLED) begin
initial begin
RAM[0] = 64'h00600100d2e3ca40;
end
end
// Read
always_ff @(posedge clk)
if(ce) dout <= #1 RAM[addr];

735
src/generic/mem/rom1p1r.sv
View File

@ -96,7 +96,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
ROM[41] = 64'h40a7853b4015551b;
ROM[42] = 64'h808210a7a02367c9;*/
ROM[0] = 64'hc001819300002197;
ROM[0] = 64'h8001819300002197;
ROM[1] = 64'h4281420141014081;
ROM[2] = 64'h4481440143814301;
ROM[3] = 64'h4681460145814501;
@ -107,7 +107,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
ROM[8] = 64'h0110011b4f814f01;
ROM[9] = 64'h059b45011161016e;
ROM[10] = 64'h0004063705fe0010;
ROM[11] = 64'h1ee000ef8006061b;
ROM[11] = 64'h1f6000ef8006061b;
ROM[12] = 64'h0ff003930000100f;
ROM[13] = 64'h4e952e3110060e37;
ROM[14] = 64'hc602829b0053f2b7;
@ -118,627 +118,116 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
ROM[19] = 64'h059bf1402573fdd0;
ROM[20] = 64'h0000061705e20870;
ROM[21] = 64'h0010029b01260613;
ROM[22] = 64'h67110002806702fe;
ROM[23] = 64'h0085179bf0070713;
ROM[24] = 64'h2781038007138ff9;
ROM[25] = 64'h7563470508a76a63;
ROM[26] = 64'h00a71733357902a7;
ROM[27] = 64'h3285350300001517;
ROM[28] = 64'h40301537e9598d79;
ROM[29] = 64'h8d7942250513051a;
ROM[30] = 64'he35d18177713e149;
ROM[31] = 64'he79300367713c295;
ROM[32] = 64'hf330674de3450207;
ROM[33] = 64'h861bc3701ff00613;
ROM[34] = 64'h01000637c730fff6;
ROM[35] = 64'hc35c674dcf10167d;
ROM[36] = 64'hd31c17fd001007b7;
ROM[37] = 64'h0007861b5b5cc30c;
ROM[38] = 64'h674d02072a23dfed;
ROM[39] = 64'h12634785fffd571c;
ROM[40] = 64'h80818793471006f6;
ROM[41] = 64'h4b10474cc3904501;
ROM[42] = 64'hc7d8c790c3cc4b58;
ROM[43] = 64'h086007138082e29d;
ROM[44] = 64'h0a90071300e50c63;
ROM[45] = 64'h0017e793f8e518e3;
ROM[46] = 64'hb74901d7e793b761;
ROM[47] = 64'h674dbfb50197e793;
ROM[48] = 64'h02072e23dffd5f5c;
ROM[49] = 64'h8513ff7d569866cd;
ROM[50] = 64'h053300a03533fff7;
ROM[51] = 64'h00a7e793808240a0;
ROM[52] = 64'h71398082557dbfa1;
ROM[53] = 64'hf8228181ca03e852;
ROM[54] = 64'hf426fc06ec4ef04a;
ROM[55] = 64'h008a7a13e05ae456;
ROM[56] = 64'h1463843289ae892a;
ROM[57] = 64'h4a8500959993000a;
ROM[58] = 64'h4549864ac4296b05;
ROM[59] = 64'h055402630009859b;
ROM[60] = 64'h008b73630004049b;
ROM[61] = 64'hecbff0ef86a66485;
ROM[62] = 64'h45814601468187aa;
ROM[63] = 64'h0207c8639c054531;
ROM[64] = 64'h0094979beb7ff0ef;
ROM[65] = 64'h0205406393811782;
ROM[66] = 64'h99ba020a1863873e;
ROM[67] = 64'ha8014501fc4d993e;
ROM[68] = 64'he93ff0ef45454685;
ROM[69] = 64'h70e24505fe055ae3;
ROM[70] = 64'h69e2790274a27442;
ROM[71] = 64'h61216b026aa26a42;
ROM[72] = 64'h9301020497138082;
ROM[73] = 64'hec26f0227179b7f9;
ROM[74] = 64'he44ef4064705e84a;
ROM[75] = 64'h842e84aad79867cd;
ROM[76] = 64'h8b85571c674d8932;
ROM[77] = 64'hd35c03600793dff5;
ROM[78] = 64'h571c674d02072423;
ROM[79] = 64'ha737b00026f3fffd;
ROM[80] = 64'h27f311f707130007;
ROM[81] = 64'hfef77de38f95b000;
ROM[82] = 64'h80018c235b1c674d;
ROM[83] = 64'he7934f5ccf9d8b89;
ROM[84] = 64'hb00026f3cf5c0027;
ROM[85] = 64'h0ff7071305f5e737;
ROM[86] = 64'h7de38f95b00027f3;
ROM[87] = 64'h9bf54f5c674dfef7;
ROM[88] = 64'h9737b00026f3cf5c;
ROM[89] = 64'h27f367f707130098;
ROM[90] = 64'hfef77de38f95b000;
ROM[91] = 64'h4501458146014681;
ROM[92] = 64'h80818993dd7ff0ef;
ROM[93] = 64'h0593460146814789;
ROM[94] = 64'h00f9882345211aa0;
ROM[95] = 64'ha783e50ddbfff0ef;
ROM[96] = 64'h17d21aa007130009;
ROM[97] = 64'h479102e79e6393d1;
ROM[98] = 64'hf0efa80900f98823;
ROM[99] = 64'ha78302054663da1f;
ROM[100]= 64'h46810207cc630009;
ROM[101]= 64'h0370051345814601;
ROM[102]= 64'h468187aad87ff0ef;
ROM[103]= 64'h0513403005b74601;
ROM[104]= 64'h8522fc07dae30a90;
ROM[105]= 64'h864a69a270a27402;
ROM[106]= 64'h614564e2694285a6;
ROM[107]= 64'hebd18b8583f9b5b9;
ROM[108]= 64'h4509458146014681;
ROM[109]= 64'hfc054de3d4fff0ef;
ROM[110]= 64'h123405b746014681;
ROM[111]= 64'h44e3d3dff0ef450d;
ROM[112]= 64'h77c10009a983fc05;
ROM[113]= 64'h460100f9f9b34681;
ROM[114]= 64'hd23ff0ef451d85ce;
ROM[115]= 64'h470567cdfa0547e3;
ROM[116]= 64'h4737b00026f3d3d8;
ROM[117]= 64'h27f323f70713000f;
ROM[118]= 64'hfef77de38f95b000;
ROM[119]= 64'h46810007ae2367cd;
ROM[120]= 64'h0370051385ce4601;
ROM[121]= 64'hf6054de3cefff0ef;
ROM[122]= 64'h0513458146014681;
ROM[123]= 64'h44e3cddff0ef0860;
ROM[124]= 64'h059346014681f605;
ROM[125]= 64'hccbff0ef45412000;
ROM[126]= 64'he7930109c783bf99;
ROM[127]= 64'hb78d00f988230087;
ROM[128]= 64'h0000000000000000;
ROM[129]= 64'h0000000000000000;
ROM[130]= 64'h0000000000000000;
ROM[131]= 64'h0000000000000000;
ROM[132]= 64'h0000000000000000;
ROM[133]= 64'h0000000000000000;
ROM[134]= 64'h0000000000000000;
ROM[135]= 64'h0000000000000000;
ROM[136]= 64'h0000000000000000;
ROM[137]= 64'h0000000000000000;
ROM[138]= 64'h0000000000000000;
ROM[139]= 64'h0000000000000000;
ROM[140]= 64'h0000000000000000;
ROM[141]= 64'h0000000000000000;
ROM[142]= 64'h0000000000000000;
ROM[143]= 64'h0000000000000000;
ROM[144]= 64'h0000000000000000;
ROM[145]= 64'h0000000000000000;
ROM[146]= 64'h0000000000000000;
ROM[147]= 64'h0000000000000000;
ROM[148]= 64'h0000000000000000;
ROM[149]= 64'h0000000000000000;
ROM[150]= 64'h0000000000000000;
ROM[151]= 64'h0000000000000000;
ROM[152]= 64'h0000000000000000;
ROM[153]= 64'h0000000000000000;
ROM[154]= 64'h0000000000000000;
ROM[155]= 64'h0000000000000000;
ROM[156]= 64'h0000000000000000;
ROM[157]= 64'h0000000000000000;
ROM[158]= 64'h0000000000000000;
ROM[159]= 64'h0000000000000000;
ROM[160]= 64'h0000000000000000;
ROM[161]= 64'h0000000000000000;
ROM[162]= 64'h0000000000000000;
ROM[163]= 64'h0000000000000000;
ROM[164]= 64'h0000000000000000;
ROM[165]= 64'h0000000000000000;
ROM[166]= 64'h0000000000000000;
ROM[167]= 64'h0000000000000000;
ROM[168]= 64'h0000000000000000;
ROM[169]= 64'h0000000000000000;
ROM[170]= 64'h0000000000000000;
ROM[171]= 64'h0000000000000000;
ROM[172]= 64'h0000000000000000;
ROM[173]= 64'h0000000000000000;
ROM[174]= 64'h0000000000000000;
ROM[175]= 64'h0000000000000000;
ROM[176]= 64'h0000000000000000;
ROM[177]= 64'h0000000000000000;
ROM[178]= 64'h0000000000000000;
ROM[179]= 64'h0000000000000000;
ROM[180]= 64'h0000000000000000;
ROM[181]= 64'h0000000000000000;
ROM[182]= 64'h0000000000000000;
ROM[183]= 64'h0000000000000000;
ROM[184]= 64'h0000000000000000;
ROM[185]= 64'h0000000000000000;
ROM[186]= 64'h0000000000000000;
ROM[187]= 64'h0000000000000000;
ROM[188]= 64'h0000000000000000;
ROM[189]= 64'h0000000000000000;
ROM[190]= 64'h0000000000000000;
ROM[191]= 64'h0000000000000000;
ROM[192]= 64'h0000000000000000;
ROM[193]= 64'h0000000000000000;
ROM[194]= 64'h0000000000000000;
ROM[195]= 64'h0000000000000000;
ROM[196]= 64'h0000000000000000;
ROM[197]= 64'h0000000000000000;
ROM[198]= 64'h0000000000000000;
ROM[199]= 64'h0000000000000000;
ROM[200]= 64'h0000000000000000;
ROM[201]= 64'h0000000000000000;
ROM[202]= 64'h0000000000000000;
ROM[203]= 64'h0000000000000000;
ROM[204]= 64'h0000000000000000;
ROM[205]= 64'h0000000000000000;
ROM[206]= 64'h0000000000000000;
ROM[207]= 64'h0000000000000000;
ROM[208]= 64'h0000000000000000;
ROM[209]= 64'h0000000000000000;
ROM[210]= 64'h0000000000000000;
ROM[211]= 64'h0000000000000000;
ROM[212]= 64'h0000000000000000;
ROM[213]= 64'h0000000000000000;
ROM[214]= 64'h0000000000000000;
ROM[215]= 64'h0000000000000000;
ROM[216]= 64'h0000000000000000;
ROM[217]= 64'h0000000000000000;
ROM[218]= 64'h0000000000000000;
ROM[219]= 64'h0000000000000000;
ROM[220]= 64'h0000000000000000;
ROM[221]= 64'h0000000000000000;
ROM[222]= 64'h0000000000000000;
ROM[223]= 64'h0000000000000000;
ROM[224]= 64'h0000000000000000;
ROM[225]= 64'h0000000000000000;
ROM[226]= 64'h0000000000000000;
ROM[227]= 64'h0000000000000000;
ROM[228]= 64'h0000000000000000;
ROM[229]= 64'h0000000000000000;
ROM[230]= 64'h0000000000000000;
ROM[231]= 64'h0000000000000000;
ROM[232]= 64'h0000000000000000;
ROM[233]= 64'h0000000000000000;
ROM[234]= 64'h0000000000000000;
ROM[235]= 64'h0000000000000000;
ROM[236]= 64'h0000000000000000;
ROM[237]= 64'h0000000000000000;
ROM[238]= 64'h0000000000000000;
ROM[239]= 64'h0000000000000000;
ROM[240]= 64'h0000000000000000;
ROM[241]= 64'h0000000000000000;
ROM[242]= 64'h0000000000000000;
ROM[243]= 64'h0000000000000000;
ROM[244]= 64'h0000000000000000;
ROM[245]= 64'h0000000000000000;
ROM[246]= 64'h0000000000000000;
ROM[247]= 64'h0000000000000000;
ROM[248]= 64'h0000000000000000;
ROM[249]= 64'h0000000000000000;
ROM[250]= 64'h0000000000000000;
ROM[251]= 64'h0000000000000000;
ROM[252]= 64'h0000000000000000;
ROM[253]= 64'h0000000000000000;
ROM[254]= 64'h0000000000000000;
ROM[255]= 64'h0000000000000000;
ROM[256]= 64'h0000000000000000;
ROM[257]= 64'h0000000000000000;
ROM[258]= 64'h0000000000000000;
ROM[259]= 64'h0000000000000000;
ROM[260]= 64'h0000000000000000;
ROM[261]= 64'h0000000000000000;
ROM[262]= 64'h0000000000000000;
ROM[263]= 64'h0000000000000000;
ROM[264]= 64'h0000000000000000;
ROM[265]= 64'h0000000000000000;
ROM[266]= 64'h0000000000000000;
ROM[267]= 64'h0000000000000000;
ROM[268]= 64'h0000000000000000;
ROM[269]= 64'h0000000000000000;
ROM[270]= 64'h0000000000000000;
ROM[271]= 64'h0000000000000000;
ROM[272]= 64'h0000000000000000;
ROM[273]= 64'h0000000000000000;
ROM[274]= 64'h0000000000000000;
ROM[275]= 64'h0000000000000000;
ROM[276]= 64'h0000000000000000;
ROM[277]= 64'h0000000000000000;
ROM[278]= 64'h0000000000000000;
ROM[279]= 64'h0000000000000000;
ROM[280]= 64'h0000000000000000;
ROM[281]= 64'h0000000000000000;
ROM[282]= 64'h0000000000000000;
ROM[283]= 64'h0000000000000000;
ROM[284]= 64'h0000000000000000;
ROM[285]= 64'h0000000000000000;
ROM[286]= 64'h0000000000000000;
ROM[287]= 64'h0000000000000000;
ROM[288]= 64'h0000000000000000;
ROM[289]= 64'h0000000000000000;
ROM[290]= 64'h0000000000000000;
ROM[291]= 64'h0000000000000000;
ROM[292]= 64'h0000000000000000;
ROM[293]= 64'h0000000000000000;
ROM[294]= 64'h0000000000000000;
ROM[295]= 64'h0000000000000000;
ROM[296]= 64'h0000000000000000;
ROM[297]= 64'h0000000000000000;
ROM[298]= 64'h0000000000000000;
ROM[299]= 64'h0000000000000000;
ROM[300]= 64'h0000000000000000;
ROM[301]= 64'h0000000000000000;
ROM[302]= 64'h0000000000000000;
ROM[303]= 64'h0000000000000000;
ROM[304]= 64'h0000000000000000;
ROM[305]= 64'h0000000000000000;
ROM[306]= 64'h0000000000000000;
ROM[307]= 64'h0000000000000000;
ROM[308]= 64'h0000000000000000;
ROM[309]= 64'h0000000000000000;
ROM[310]= 64'h0000000000000000;
ROM[311]= 64'h0000000000000000;
ROM[312]= 64'h0000000000000000;
ROM[313]= 64'h0000000000000000;
ROM[314]= 64'h0000000000000000;
ROM[315]= 64'h0000000000000000;
ROM[316]= 64'h0000000000000000;
ROM[317]= 64'h0000000000000000;
ROM[318]= 64'h0000000000000000;
ROM[319]= 64'h0000000000000000;
ROM[320]= 64'h0000000000000000;
ROM[321]= 64'h0000000000000000;
ROM[322]= 64'h0000000000000000;
ROM[323]= 64'h0000000000000000;
ROM[324]= 64'h0000000000000000;
ROM[325]= 64'h0000000000000000;
ROM[326]= 64'h0000000000000000;
ROM[327]= 64'h0000000000000000;
ROM[328]= 64'h0000000000000000;
ROM[329]= 64'h0000000000000000;
ROM[330]= 64'h0000000000000000;
ROM[331]= 64'h0000000000000000;
ROM[332]= 64'h0000000000000000;
ROM[333]= 64'h0000000000000000;
ROM[334]= 64'h0000000000000000;
ROM[335]= 64'h0000000000000000;
ROM[336]= 64'h0000000000000000;
ROM[337]= 64'h0000000000000000;
ROM[338]= 64'h0000000000000000;
ROM[339]= 64'h0000000000000000;
ROM[340]= 64'h0000000000000000;
ROM[341]= 64'h0000000000000000;
ROM[342]= 64'h0000000000000000;
ROM[343]= 64'h0000000000000000;
ROM[344]= 64'h0000000000000000;
ROM[345]= 64'h0000000000000000;
ROM[346]= 64'h0000000000000000;
ROM[347]= 64'h0000000000000000;
ROM[348]= 64'h0000000000000000;
ROM[349]= 64'h0000000000000000;
ROM[350]= 64'h0000000000000000;
ROM[351]= 64'h0000000000000000;
ROM[352]= 64'h0000000000000000;
ROM[353]= 64'h0000000000000000;
ROM[354]= 64'h0000000000000000;
ROM[355]= 64'h0000000000000000;
ROM[356]= 64'h0000000000000000;
ROM[357]= 64'h0000000000000000;
ROM[358]= 64'h0000000000000000;
ROM[359]= 64'h0000000000000000;
ROM[360]= 64'h0000000000000000;
ROM[361]= 64'h0000000000000000;
ROM[362]= 64'h0000000000000000;
ROM[363]= 64'h0000000000000000;
ROM[364]= 64'h0000000000000000;
ROM[365]= 64'h0000000000000000;
ROM[366]= 64'h0000000000000000;
ROM[367]= 64'h0000000000000000;
ROM[368]= 64'h0000000000000000;
ROM[369]= 64'h0000000000000000;
ROM[370]= 64'h0000000000000000;
ROM[371]= 64'h0000000000000000;
ROM[372]= 64'h0000000000000000;
ROM[373]= 64'h0000000000000000;
ROM[374]= 64'h0000000000000000;
ROM[375]= 64'h0000000000000000;
ROM[376]= 64'h0000000000000000;
ROM[377]= 64'h0000000000000000;
ROM[378]= 64'h0000000000000000;
ROM[379]= 64'h0000000000000000;
ROM[380]= 64'h0000000000000000;
ROM[381]= 64'h0000000000000000;
ROM[382]= 64'h0000000000000000;
ROM[383]= 64'h0000000000000000;
ROM[384]= 64'h0000000000000000;
ROM[385]= 64'h0000000000000000;
ROM[386]= 64'h0000000000000000;
ROM[387]= 64'h0000000000000000;
ROM[388]= 64'h0000000000000000;
ROM[389]= 64'h0000000000000000;
ROM[390]= 64'h0000000000000000;
ROM[391]= 64'h0000000000000000;
ROM[392]= 64'h0000000000000000;
ROM[393]= 64'h0000000000000000;
ROM[394]= 64'h0000000000000000;
ROM[395]= 64'h0000000000000000;
ROM[396]= 64'h0000000000000000;
ROM[397]= 64'h0000000000000000;
ROM[398]= 64'h0000000000000000;
ROM[399]= 64'h0000000000000000;
ROM[400]= 64'h0000000000000000;
ROM[401]= 64'h0000000000000000;
ROM[402]= 64'h0000000000000000;
ROM[403]= 64'h0000000000000000;
ROM[404]= 64'h0000000000000000;
ROM[405]= 64'h0000000000000000;
ROM[406]= 64'h0000000000000000;
ROM[407]= 64'h0000000000000000;
ROM[408]= 64'h0000000000000000;
ROM[409]= 64'h0000000000000000;
ROM[410]= 64'h0000000000000000;
ROM[411]= 64'h0000000000000000;
ROM[412]= 64'h0000000000000000;
ROM[413]= 64'h0000000000000000;
ROM[414]= 64'h0000000000000000;
ROM[415]= 64'h0000000000000000;
ROM[416]= 64'h0000000000000000;
ROM[417]= 64'h0000000000000000;
ROM[418]= 64'h0000000000000000;
ROM[419]= 64'h0000000000000000;
ROM[420]= 64'h0000000000000000;
ROM[421]= 64'h0000000000000000;
ROM[422]= 64'h0000000000000000;
ROM[423]= 64'h0000000000000000;
ROM[424]= 64'h0000000000000000;
ROM[425]= 64'h0000000000000000;
ROM[426]= 64'h0000000000000000;
ROM[427]= 64'h0000000000000000;
ROM[428]= 64'h0000000000000000;
ROM[429]= 64'h0000000000000000;
ROM[430]= 64'h0000000000000000;
ROM[431]= 64'h0000000000000000;
ROM[432]= 64'h0000000000000000;
ROM[433]= 64'h0000000000000000;
ROM[434]= 64'h0000000000000000;
ROM[435]= 64'h0000000000000000;
ROM[436]= 64'h0000000000000000;
ROM[437]= 64'h0000000000000000;
ROM[438]= 64'h0000000000000000;
ROM[439]= 64'h0000000000000000;
ROM[440]= 64'h0000000000000000;
ROM[441]= 64'h0000000000000000;
ROM[442]= 64'h0000000000000000;
ROM[443]= 64'h0000000000000000;
ROM[444]= 64'h0000000000000000;
ROM[445]= 64'h0000000000000000;
ROM[446]= 64'h0000000000000000;
ROM[447]= 64'h0000000000000000;
ROM[448]= 64'h0000000000000000;
ROM[449]= 64'h0000000000000000;
ROM[450]= 64'h0000000000000000;
ROM[451]= 64'h0000000000000000;
ROM[452]= 64'h0000000000000000;
ROM[453]= 64'h0000000000000000;
ROM[454]= 64'h0000000000000000;
ROM[455]= 64'h0000000000000000;
ROM[456]= 64'h0000000000000000;
ROM[457]= 64'h0000000000000000;
ROM[458]= 64'h0000000000000000;
ROM[459]= 64'h0000000000000000;
ROM[460]= 64'h0000000000000000;
ROM[461]= 64'h0000000000000000;
ROM[462]= 64'h0000000000000000;
ROM[463]= 64'h0000000000000000;
ROM[464]= 64'h0000000000000000;
ROM[465]= 64'h0000000000000000;
ROM[466]= 64'h0000000000000000;
ROM[467]= 64'h0000000000000000;
ROM[468]= 64'h0000000000000000;
ROM[469]= 64'h0000000000000000;
ROM[470]= 64'h0000000000000000;
ROM[471]= 64'h0000000000000000;
ROM[472]= 64'h0000000000000000;
ROM[473]= 64'h0000000000000000;
ROM[474]= 64'h0000000000000000;
ROM[475]= 64'h0000000000000000;
ROM[476]= 64'h0000000000000000;
ROM[477]= 64'h0000000000000000;
ROM[478]= 64'h0000000000000000;
ROM[479]= 64'h0000000000000000;
ROM[480]= 64'h0000000000000000;
ROM[481]= 64'h0000000000000000;
ROM[482]= 64'h0000000000000000;
ROM[483]= 64'h0000000000000000;
ROM[484]= 64'h0000000000000000;
ROM[485]= 64'h0000000000000000;
ROM[486]= 64'h0000000000000000;
ROM[487]= 64'h0000000000000000;
ROM[488]= 64'h0000000000000000;
ROM[489]= 64'h0000000000000000;
ROM[490]= 64'h0000000000000000;
ROM[491]= 64'h0000000000000000;
ROM[492]= 64'h0000000000000000;
ROM[493]= 64'h0000000000000000;
ROM[494]= 64'h0000000000000000;
ROM[495]= 64'h0000000000000000;
ROM[496]= 64'h0000000000000000;
ROM[497]= 64'h0000000000000000;
ROM[498]= 64'h0000000000000000;
ROM[499]= 64'h0000000000000000;
ROM[500]= 64'h0000000000000000;
ROM[501]= 64'h0000000000000000;
ROM[502]= 64'h0000000000000000;
ROM[503]= 64'h0000000000000000;
ROM[504]= 64'h0000000000000000;
ROM[505]= 64'h0000000000000000;
ROM[506]= 64'h0000000000000000;
ROM[507]= 64'h0000000000000000;
ROM[508]= 64'h0000000000000000;
ROM[509]= 64'h0000000000000000;
ROM[510]= 64'h0000000000000000;
ROM[511]= 64'h0000000000000000;
ROM[512]= 64'h0000000000000000;
ROM[513]= 64'h0000000000000000;
ROM[514]= 64'h0000000000000000;
ROM[515]= 64'h0000000000000000;
ROM[516]= 64'h0000000000000000;
ROM[517]= 64'h0000000000000000;
ROM[518]= 64'h0000000000000000;
ROM[519]= 64'h0000000000000000;
ROM[520]= 64'h0000000000000000;
ROM[521]= 64'h0000000000000000;
ROM[522]= 64'h0000000000000000;
ROM[523]= 64'h0000000000000000;
ROM[524]= 64'h0000000000000000;
ROM[525]= 64'h0000000000000000;
ROM[526]= 64'h0000000000000000;
ROM[527]= 64'h0000000000000000;
ROM[528]= 64'h0000000000000000;
ROM[529]= 64'h0000000000000000;
ROM[530]= 64'h0000000000000000;
ROM[531]= 64'h0000000000000000;
ROM[532]= 64'h0000000000000000;
ROM[533]= 64'h0000000000000000;
ROM[534]= 64'h0000000000000000;
ROM[535]= 64'h0000000000000000;
ROM[536]= 64'h0000000000000000;
ROM[537]= 64'h0000000000000000;
ROM[538]= 64'h0000000000000000;
ROM[539]= 64'h0000000000000000;
ROM[540]= 64'h0000000000000000;
ROM[541]= 64'h0000000000000000;
ROM[542]= 64'h0000000000000000;
ROM[543]= 64'h0000000000000000;
ROM[544]= 64'h0000000000000000;
ROM[545]= 64'h0000000000000000;
ROM[546]= 64'h0000000000000000;
ROM[547]= 64'h0000000000000000;
ROM[548]= 64'h0000000000000000;
ROM[549]= 64'h0000000000000000;
ROM[550]= 64'h0000000000000000;
ROM[551]= 64'h0000000000000000;
ROM[552]= 64'h0000000000000000;
ROM[553]= 64'h0000000000000000;
ROM[554]= 64'h0000000000000000;
ROM[555]= 64'h0000000000000000;
ROM[556]= 64'h0000000000000000;
ROM[557]= 64'h0000000000000000;
ROM[558]= 64'h0000000000000000;
ROM[559]= 64'h0000000000000000;
ROM[560]= 64'h0000000000000000;
ROM[561]= 64'h0000000000000000;
ROM[562]= 64'h0000000000000000;
ROM[563]= 64'h0000000000000000;
ROM[564]= 64'h0000000000000000;
ROM[565]= 64'h0000000000000000;
ROM[566]= 64'h0000000000000000;
ROM[567]= 64'h0000000000000000;
ROM[568]= 64'h0000000000000000;
ROM[569]= 64'h0000000000000000;
ROM[570]= 64'h0000000000000000;
ROM[571]= 64'h0000000000000000;
ROM[572]= 64'h0000000000000000;
ROM[573]= 64'h0000000000000000;
ROM[574]= 64'h0000000000000000;
ROM[575]= 64'h0000000000000000;
ROM[576]= 64'h0000000000000000;
ROM[577]= 64'h0000000000000000;
ROM[578]= 64'h0000000000000000;
ROM[579]= 64'h0000000000000000;
ROM[580]= 64'h0000000000000000;
ROM[581]= 64'h0000000000000000;
ROM[582]= 64'h0000000000000000;
ROM[583]= 64'h0000000000000000;
ROM[584]= 64'h0000000000000000;
ROM[585]= 64'h0000000000000000;
ROM[586]= 64'h0000000000000000;
ROM[587]= 64'h0000000000000000;
ROM[588]= 64'h0000000000000000;
ROM[589]= 64'h0000000000000000;
ROM[590]= 64'h0000000000000000;
ROM[591]= 64'h0000000000000000;
ROM[592]= 64'h0000000000000000;
ROM[593]= 64'h0000000000000000;
ROM[594]= 64'h0000000000000000;
ROM[595]= 64'h0000000000000000;
ROM[596]= 64'h0000000000000000;
ROM[597]= 64'h0000000000000000;
ROM[598]= 64'h0000000000000000;
ROM[599]= 64'h0000000000000000;
ROM[600]= 64'h0000000000000000;
ROM[601]= 64'h0000000000000000;
ROM[602]= 64'h0000000000000000;
ROM[603]= 64'h0000000000000000;
ROM[604]= 64'h0000000000000000;
ROM[605]= 64'h0000000000000000;
ROM[606]= 64'h0000000000000000;
ROM[607]= 64'h0000000000000000;
ROM[608]= 64'h0000000000000000;
ROM[609]= 64'h0000000000000000;
ROM[610]= 64'h0000000000000000;
ROM[611]= 64'h0000000000000000;
ROM[612]= 64'h0000000000000000;
ROM[613]= 64'h0000000000000000;
ROM[614]= 64'h0000000000000000;
ROM[615]= 64'h0000000000000000;
ROM[616]= 64'h0000000000000000;
ROM[617]= 64'h0000000000000000;
ROM[618]= 64'h0000000000000000;
ROM[619]= 64'h0000000000000000;
ROM[620]= 64'h0000000000000000;
ROM[621]= 64'h0000000000000000;
ROM[622]= 64'h0000000000000000;
ROM[623]= 64'h0000000000000000;
ROM[624]= 64'h0000000000000000;
ROM[625]= 64'h0000000000000000;
ROM[626]= 64'h0000000000000000;
ROM[627]= 64'h0000000000000000;
ROM[628]= 64'h0000000000000000;
ROM[629]= 64'h0000000000000000;
ROM[630]= 64'h0000000000000000;
ROM[631]= 64'h0000000000000000;
ROM[632]= 64'h0000000000000000;
ROM[633]= 64'h0000000000000000;
ROM[634]= 64'h0000000000000000;
ROM[635]= 64'h0000000000000000;
ROM[636]= 64'h0000000000000000;
ROM[637]= 64'h0000000000000000;
ROM[638]= 64'h0000000000000000;
ROM[639]= 64'h0000000000000000;
ROM[640]= 64'h00600100d2e3ca40;
end
end
ROM[22] = 64'h68110002806702fe;
ROM[23] = 64'h0085179bf0080813;
ROM[24] = 64'h038008130107f7b3;
ROM[25] = 64'h480508a86c632781;
ROM[26] = 64'h1533357902a87963;
ROM[27] = 64'h38030000181700a8;
ROM[28] = 64'h1c6301057833f268;
ROM[29] = 64'h081a403018370808;
ROM[30] = 64'h0105783342280813;
ROM[31] = 64'h1815751308081063;
ROM[32] = 64'h00367513c295e14d;
ROM[33] = 64'h654ded510207e793;
ROM[34] = 64'hc1701ff00613f130;
ROM[35] = 64'h0637c530fff6861b;
ROM[36] = 64'h664dcd10167d0200;
ROM[37] = 64'h17fd001007b7c25c;
ROM[38] = 64'h859b5a5cc20cd21c;
ROM[39] = 64'h02062a23dfed0007;
ROM[40] = 64'h4785fffd561c664d;
ROM[41] = 64'h4501461c06f59063;
ROM[42] = 64'h4a1cc35c465cc31c;
ROM[43] = 64'he29dc75c4a5cc71c;
ROM[44] = 64'h0c63086008138082;
ROM[45] = 64'h1ae30a9008130105;
ROM[46] = 64'hb7710017e793f905;
ROM[47] = 64'he793b75901d7e793;
ROM[48] = 64'h5f5c674db7410197;
ROM[49] = 64'h66cd02072e23dffd;
ROM[50] = 64'hfff78513ff7d5698;
ROM[51] = 64'h40a0053300a03533;
ROM[52] = 64'hbfb100a7e7938082;
ROM[53] = 64'he0a2715d8082557d;
ROM[54] = 64'he486f052f44ef84a;
ROM[55] = 64'hfa13e85aec56fc26;
ROM[56] = 64'h843289ae892a0086;
ROM[57] = 64'h00959993000a1463;
ROM[58] = 64'h864ac4396b054a85;
ROM[59] = 64'h0009859b4549870a;
ROM[60] = 64'h0004049b05540363;
ROM[61] = 64'h86a66485008b7363;
ROM[62] = 64'h870a87aaec7ff0ef;
ROM[63] = 64'h4531458146014681;
ROM[64] = 64'hf0ef0207c9639c05;
ROM[65] = 64'h17820094979beb1f;
ROM[66] = 64'h873e020541639381;
ROM[67] = 64'h993e99ba020a1963;
ROM[68] = 64'h870aa8094501f85d;
ROM[69] = 64'he8bff0ef45454685;
ROM[70] = 64'h60a64505fe0559e3;
ROM[71] = 64'h79a2794274e26406;
ROM[72] = 64'h61616b426ae27a02;
ROM[73] = 64'h9301020497138082;
ROM[74] = 64'hf426f8227139b7f1;
ROM[75] = 64'hec4efc064705f04a;
ROM[76] = 64'h84aad79867cde852;
ROM[77] = 64'h571c674d8932842e;
ROM[78] = 64'h03600793dff58b85;
ROM[79] = 64'h674d02072423d35c;
ROM[80] = 64'hb00026f3fffd571c;
ROM[81] = 64'h11f707130007a737;
ROM[82] = 64'h7de38f95b00027f3;
ROM[83] = 64'h8b895b1c674dfef7;
ROM[84] = 64'h0027e7934f5ccf9d;
ROM[85] = 64'he737b00026f3cf5c;
ROM[86] = 64'h27f30ff7071305f5;
ROM[87] = 64'hfef77de38f95b000;
ROM[88] = 64'hcf5c9bf54f5c674d;
ROM[89] = 64'h00989737b00026f3;
ROM[90] = 64'hb00027f367f70713;
ROM[91] = 64'h4681fef77de38f95;
ROM[92] = 64'h4501870a45814601;
ROM[93] = 64'h4681870adcfff0ef;
ROM[94] = 64'h45211aa005934601;
ROM[95] = 64'h4782e12ddbfff0ef;
ROM[96] = 64'h17d249911aa00713;
ROM[97] = 64'h099302e7876393d1;
ROM[98] = 64'h70e2744285220ff0;
ROM[99] = 64'h69e2864a86ce6a42;
ROM[100]= 64'h612174a285a67902;
ROM[101]= 64'h40e3d8dff0efb551;
ROM[102]= 64'h0207c7634782fe05;
ROM[103]= 64'h458146014681870a;
ROM[104]= 64'hd73ff0ef03700513;
ROM[105]= 64'h46014681870a87aa;
ROM[106]= 64'h0a900513403005b7;
ROM[107]= 64'h4989bf4dfc07d9e3;
ROM[108]= 64'hc3998b8583f9bfe1;
ROM[109]= 64'h4681870a0089e993;
ROM[110]= 64'hf0ef450945814601;
ROM[111]= 64'h870af8054ae3d41f;
ROM[112]= 64'h123405b746014681;
ROM[113]= 64'h40e3d2dff0ef450d;
ROM[114]= 64'h870a77c14a02f805;
ROM[115]= 64'h4601468100fa7a33;
ROM[116]= 64'hd13ff0ef451d85d2;
ROM[117]= 64'h470567cdf60543e3;
ROM[118]= 64'h4737b00026f3d3d8;
ROM[119]= 64'h27f323f70713000f;
ROM[120]= 64'hfef77de38f95b000;
ROM[121]= 64'h870a0007ae2367cd;
ROM[122]= 64'h051385d246014681;
ROM[123]= 64'h48e3cddff0ef0370;
ROM[124]= 64'h46014681870af205;
ROM[125]= 64'hf0ef086005134581;
ROM[126]= 64'h870af0054ee3cc9f;
ROM[127]= 64'h2000059346014681;
ROM[128]= 64'h56e3cb5ff0ef4541;
ROM[129]= 64'h00000000b711f005;
end // initial begin
end // if (PRELOAD_ENABLED)
end
endmodule

1
src/mmu/adrdecs.sv
View File

@ -51,7 +51,6 @@ module adrdecs (
adrdec newsdc(PhysicalAddress, `SDC2_BASE, `SDC2_RANGE, `SDC2_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]);
assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected
endmodule
// verilator lint_on UNOPTFLAT

2
src/uncore/ram_ahb.sv
View File

@ -71,7 +71,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
mux2 #(`PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
// single-ported RAM
ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1),
ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN), .PRELOAD_ENABLED(`FPGA)) memory(.clk(HCLK), .ce(1'b1),
.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));

60
src/uncore/uncore.sv
View File

@ -33,30 +33,31 @@
// *** and use memread signal to reduce power when reads aren't needed
module uncore (
// AHB Bus Interface
input logic HCLK, HRESETn,
input logic TIMECLK,
input logic [`PA_BITS-1:0] HADDR,
input logic [`AHBW-1:0] HWDATA,
input logic [`XLEN/8-1:0] HWSTRB,
input logic HWRITE,
input logic [2:0] HSIZE,
input logic [2:0] HBURST,
input logic [3:0] HPROT,
input logic [1:0] HTRANS,
input logic HMASTLOCK,
input logic [`AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic [`AHBW-1:0] HRDATA,
output logic HREADY, HRESP,
output logic HSELEXT,
input logic HCLK, HRESETn,
input logic TIMECLK,
input logic [`PA_BITS-1:0] HADDR,
input logic [`AHBW-1:0] HWDATA,
input logic [`XLEN/8-1:0] HWSTRB,
input logic HWRITE,
input logic [2:0] HSIZE,
input logic [2:0] HBURST,
input logic [3:0] HPROT,
input logic [1:0] HTRANS,
input logic HMASTLOCK,
input logic [`AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic [`AHBW-1:0] HRDATA,
output logic HREADY, HRESP,
output logic HSELEXT,
output logic HSELEXTSDC,
// peripheral pins
output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT
output logic MExtInt, SExtInt, // External interrupts from PLIC
output logic [63:0] MTIME_CLINT, // MTIME, from CLINT
input logic [31:0] GPIOPinsIn, // GPIO pin input value
output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable
input logic UARTSin, // UART serial input
output logic UARTSout // UART serial output
output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT
output logic MExtInt, SExtInt, // External interrupts from PLIC
output logic [63:0] MTIME_CLINT, // MTIME, from CLINT
input logic [31:0] GPIOPinsIn, // GPIO pin input value
output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable
input logic UARTSin, // UART serial input
output logic UARTSout // UART serial output
/*output logic SDCCmdOut, // SD Card command output
output logic SDCCmdOE, // SD Card command output enable
input logic SDCCmdIn, // SD Card command input
@ -87,13 +88,16 @@ module uncore (
logic [`XLEN-1:0] HREADBRIDGE;
logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
(* mark_debug = "true" *) logic HSELEXTSDCD;
// Determine which region of physical memory (if any) is being accessed
// Use a trimmed down portion of the PMA checker - only the address decoders
// Set access types to all 1 as don't cares because the MMU has already done access checking
adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
// unswizzle HSEL signals
assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[10:1];
assign {HSELEXTSDC, HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[11:1];
// AHB -> APB bridge
ahbapbbridge #(4) ahbapbbridge (
@ -168,19 +172,19 @@ module uncore (
// AHB Read Multiplexer
assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
({`XLEN{HSELEXTD}} & HRDATAEXT) |
({`XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) |
({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
({`XLEN{HSELBootRomD}} & HREADBootRom) |
({`XLEN{HSELSDCD}} & HREADSDC);
assign HRESP = HSELRamD & HRESPRam |
HSELEXTD & HRESPEXT |
(HSELEXTD | HSELEXTSDCD) & HRESPEXT |
HSELBRIDGE & HRESPBRIDGE |
HSELBootRomD & HRESPBootRom |
HSELSDC & HRESPSDC;
assign HREADY = HSELRamD & HREADYRam |
HSELEXTD & HREADYEXT |
(HSELEXTD | HSELEXTSDCD) & HREADYEXT |
HSELBRIDGED & HREADYBRIDGE |
HSELBootRomD & HREADYBootRom |
HSELSDCD & HREADYSDC |
@ -191,7 +195,7 @@ module uncore (
// takes more than 1 cycle to repsond it needs to hold on to the old select until the
// device is ready. Hense this register must be selectively enabled by HREADY.
// However on reset None must be seleted.
flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:0], 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[11:0], 11'b1, {HSELEXTSDCD, HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
endmodule

49
src/wally/wallypipelinedsoc.sv
View File

@ -30,32 +30,33 @@
`include "wally-config.vh"
module wallypipelinedsoc (
input logic clk,
input logic reset_ext, // external asynchronous reset pin
output logic reset, // reset synchronized to clk to prevent races on release
input logic clk,
input logic reset_ext, // external asynchronous reset pin
output logic reset, // reset synchronized to clk to prevent races on release
// AHB Interface
input logic [`AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic HSELEXT,
input logic [`AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic HSELEXT,
output logic HSELEXTSDC,
// outputs to external memory, shared with uncore memory
output logic HCLK, HRESETn,
output logic [`PA_BITS-1:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK,
output logic HREADY,
output logic HCLK, HRESETn,
output logic [`PA_BITS-1:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK,
output logic HREADY,
// I/O Interface
input logic TIMECLK, // optional for CLINT MTIME counter
input logic [31:0] GPIOPinsIn, // inputs from GPIO
output logic [31:0] GPIOPinsOut, // output values for GPIO
output logic [31:0] GPIOPinsEn, // output enables for GPIO
input logic UARTSin, // UART serial data input
output logic UARTSout // UART serial data output
input logic TIMECLK, // optional for CLINT MTIME counter
input logic [31:0] GPIOPinsIn, // inputs from GPIO
output logic [31:0] GPIOPinsOut, // output values for GPIO
output logic [31:0] GPIOPinsEn, // output enables for GPIO
input logic UARTSin, // UART serial data input
output logic UARTSout // UART serial data output
/*input logic SDCCmdIn, // SDC Command input
output logic SDCCmdOut, // SDC Command output
output logic SDCCmdOE, // SDC Command output enable
@ -84,7 +85,7 @@ module wallypipelinedsoc (
if (`BUS_SUPPORTED) begin : uncore
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin,
.UARTSout, .MTIME_CLINT
/*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/);

85
tests/custom/boot/boot.c
View File

@ -116,15 +116,17 @@ struct sdc_regs {
#define MAX_BLOCK_CNT 0x1000
static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000;
#define SDC 0x00013000;
static int errno __attribute__((section(".bss")));
// static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000;
// static int errno __attribute__((section(".bss")));
// static DSTATUS drv_status __attribute__((section(".bss")));
static BYTE card_type __attribute__((section(".bss")));
static uint32_t response[4] __attribute__((section(".bss")));
static int alt_mem __attribute__((section(".bss")));
// static BYTE card_type __attribute__((section(".bss")));
// static uint32_t response[4] __attribute__((section(".bss")));
// static int alt_mem __attribute__((section(".bss")));
static const char * errno_to_str(void) {
/*static const char * errno_to_str(void) {
switch (errno) {
case ERR_EOF: return "Unexpected EOF";
case ERR_NOT_ELF: return "Not an ELF file";
@ -139,7 +141,7 @@ static const char * errno_to_str(void) {
case FR_TIMEOUT: return "Timeout";
}
return "Unknown error code";
}
}*/
static void usleep(unsigned us) {
uintptr_t cycles0;
@ -151,7 +153,9 @@ static void usleep(unsigned us) {
}
}
static int sdc_cmd_finish(unsigned cmd) {
static int sdc_cmd_finish(unsigned cmd, uint32_t * response) {
struct sdc_regs * regs = (struct sdc_regs *)SDC;
while (1) {
unsigned status = regs->cmd_int_status;
if (status) {
@ -166,10 +170,10 @@ static int sdc_cmd_finish(unsigned cmd) {
response[3] = regs->response4;
return 0;
}
errno = FR_DISK_ERR;
/* errno = FR_DISK_ERR;
if (status & SDC_CMD_INT_STATUS_CTE) errno = FR_TIMEOUT;
if (status & SDC_CMD_INT_STATUS_CCRC) errno = ERR_CMD_CRC;
if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK;
if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK;*/
break;
}
}
@ -178,21 +182,24 @@ static int sdc_cmd_finish(unsigned cmd) {
static int sdc_data_finish(void) {
int status;
struct sdc_regs * regs = (struct sdc_regs *)SDC;
while ((status = regs->dat_int_status) == 0) {}
regs->dat_int_status = 0;
while (regs->software_reset != 0) {}
if (status == SDC_DAT_INT_STATUS_TRS) return 0;
errno = FR_DISK_ERR;
/* errno = FR_DISK_ERR;
if (status & SDC_DAT_INT_STATUS_CTE) errno = FR_TIMEOUT;
if (status & SDC_DAT_INT_STATUS_CRC) errno = ERR_DATA_CRC;
if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO;
if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO;*/
return -1;
}
static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks) {
unsigned command = (cmd & 0x3f) << 8;
static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks, uint32_t * response) {
struct sdc_regs * regs = (struct sdc_regs *)SDC;
unsigned command = (cmd & 0x3f) << 8;
switch (cmd) {
case CMD0:
case CMD4:
@ -262,29 +269,32 @@ static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks
if (blocks) {
command |= 1 << 5;
if ((intptr_t)buf & 3) {
errno = ERR_BUF_ALIGNMENT;
// errno = ERR_BUF_ALIGNMENT;
return -1;
}
regs->dma_addres = (uint64_t)(intptr_t)buf;
regs->block_size = 511;
regs->block_count = blocks - 1;
regs->data_timeout = 0xFFFFFF;
regs->data_timeout = 0x1FFFFFF;
}
regs->command = command;
regs->cmd_timeout = 0xFFFFF;
regs->argument = arg;
if (sdc_cmd_finish(cmd) < 0) return -1;
if (sdc_cmd_finish(cmd, response) < 0) return -1;
if (blocks) return sdc_data_finish();
return 0;
}
#define send_cmd(cmd, arg) send_data_cmd(cmd, arg, NULL, 0)
#define send_cmd(cmd, arg, response) send_data_cmd(cmd, arg, NULL, 0, response)
static int ini_sd(void) {
static BYTE ini_sd(void) {
struct sdc_regs * regs = (struct sdc_regs *)SDC;
unsigned rca;
BYTE card_type;
uint32_t response[4];
/* Reset controller */
regs->software_reset = 1;
@ -311,12 +321,12 @@ static int ini_sd(void) {
}
/* Enter Idle state */
send_cmd(CMD0, 0);
send_cmd(CMD0, 0, response);
card_type = CT_SD1;
if (send_cmd(CMD8, 0x1AA) == 0) {
if (send_cmd(CMD8, 0x1AA, response) == 0) {
if ((response[0] & 0xfff) != 0x1AA) {
errno = ERR_CMD_CHECK;
// errno = ERR_CMD_CHECK;
return -1;
}
card_type = CT_SD2;
@ -325,7 +335,7 @@ static int ini_sd(void) {
/* Wait for leaving idle state (ACMD41 with HCS bit) */
while (1) {
/* ACMD41, Set Operating Conditions: Host High Capacity & 3.3V */
if (send_cmd(CMD55, 0) < 0 || send_cmd(ACMD41, 0x40300000) < 0) return -1;
if (send_cmd(CMD55, 0, response) < 0 || send_cmd(ACMD41, 0x40300000, response) < 0) return -1;
if (response[0] & (1 << 31)) {
if (response[0] & (1 << 30)) card_type |= CT_BLOCK;
break;
@ -333,15 +343,15 @@ static int ini_sd(void) {
}
/* Enter Identification state */
if (send_cmd(CMD2, 0) < 0) return -1;
if (send_cmd(CMD2, 0, response) < 0) return -1;
/* Get RCA (Relative Card Address) */
rca = 0x1234;
if (send_cmd(CMD3, rca << 16) < 0) return -1;
if (send_cmd(CMD3, rca << 16, response) < 0) return -1;
rca = response[0] >> 16;
/* Select card */
if (send_cmd(CMD7, rca << 16) < 0) return -1;
if (send_cmd(CMD7, rca << 16, response) < 0) return -1;
/* Clock 25MHz */
// 22Mhz/2 = 11Mhz
@ -350,16 +360,16 @@ static int ini_sd(void) {
/* Bus width 1-bit */
regs->control = 0;
if (send_cmd(CMD55, rca << 16) < 0 || send_cmd(ACMD6, 0) < 0) return -1;
if (send_cmd(CMD55, rca << 16, response) < 0 || send_cmd(ACMD6, 0, response) < 0) return -1;
/* Set R/W block length to 512 */
if (send_cmd(CMD16, 512) < 0) return -1;
if (send_cmd(CMD16, 512, response) < 0) return -1;
// drv_status &= ~STA_NOINIT;
return 0;
return card_type;
}
int disk_read(BYTE * buf, LBA_t sector, UINT count) {
int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) {
/* This is not needed. This has everything to do with the FAT
filesystem stuff that I'm not including. All I need to do is
@ -370,13 +380,16 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
// if (!count) return RES_PARERR;
/* if (drv_status & STA_NOINIT) return RES_NOTRDY; */
uint32_t response[4];
struct sdc_regs * regs = (struct sdc_regs *)SDC;
/* Convert LBA to byte address if needed */
if (!(card_type & CT_BLOCK)) sector *= 512;
while (count > 0) {
UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count;
unsigned bytes = bcnt * 512;
if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return 1;
if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return 1;
if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt, response) < 0) return 1;
if (bcnt > 1 && send_cmd(CMD12, 0, response) < 0) return 1;
sector += (card_type & CT_BLOCK) ? bcnt : bytes;
count -= bcnt;
buf += bytes;
@ -386,11 +399,13 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
}
void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
ini_sd();
BYTE card_type;
card_type = ini_sd();
BYTE * buf = (BYTE *)Dst;
if (disk_read(buf, (LBA_t)address, (UINT)numBlocks) < 0) /* UART Print function?*/;
if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/;
}
/*

1
tests/custom/linker1000.x
View File

@ -72,6 +72,7 @@ SECTIONS
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = 0x0000000000002000;
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.sdata2 :