mirror of
https://github.com/openhwgroup/cvw
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Update ifu.sv
Program clean up
This commit is contained in:
Harshini Srinath
GitHub
parent
b5c655b1c3
commit
a5561c2cf6
191
src/ifu/ifu.sv
191
src/ifu/ifu.sv
@ -26,116 +26,115 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ifu import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
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// Command from CPU
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input logic InvalidateICacheM, // Clears all instruction cache valid bits
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input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
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input logic InstrValidD, InstrValidE, InstrValidM,
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input logic BranchD, BranchE,
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input logic JumpD, JumpE,
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input logic InvalidateICacheM, // Clears all instruction cache valid bits
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input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
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input logic InstrValidD, InstrValidE, InstrValidM,
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input logic BranchD, BranchE,
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input logic JumpD, JumpE,
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// Bus interface
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output logic [P.PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU
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input logic [P.XLEN-1:0] HRDATA, // Bus read data from IFU to EBU
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input logic IFUHREADY, // Bus ready from IFU to EBU
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output logic IFUHWRITE, // Bus write operation from IFU to EBU
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output logic [2:0] IFUHSIZE, // Bus operation size from IFU to EBU
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output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU
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output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU
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input logic IFUHREADY, // Bus ready from IFU to EBU
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output logic IFUHWRITE, // Bus write operation from IFU to EBU
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output logic [2:0] IFUHSIZE, // Bus operation size from IFU to EBU
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output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU
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output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU
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output logic [P.XLEN-1:0] PCSpillF, // PCF with possible + 2 to handle spill to HPTW
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// Execute
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output logic [P.XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
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input logic PCSrcE, // Executation stage branch is taken
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input logic PCSrcE, // Executation stage branch is taken
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input logic [P.XLEN-1:0] IEUAdrE, // The branch/jump target address
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input logic [P.XLEN-1:0] IEUAdrM, // The branch/jump target address
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output logic [P.XLEN-1:0] PCE, // Execution stage instruction address
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output logic BPWrongE, // Prediction is wrong
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output logic BPWrongM, // Prediction is wrong
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output logic BPWrongE, // Prediction is wrong
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output logic BPWrongM, // Prediction is wrong
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// Mem
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output logic CommittedF, // I$ or bus memory operation started, delay interrupts
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output logic CommittedF, // I$ or bus memory operation started, delay interrupts
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input logic [P.XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes.
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output logic [P.XLEN-1:0] PC2NextF, // Selected PC between branch prediction and next valid PC if CSRWriteFence
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output logic [31:0] InstrD, // The decoded instruction in Decode stage
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output logic [31:0] InstrM, // The decoded instruction in Memory stage
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output logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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output logic [31:0] InstrD, // The decoded instruction in Decode stage
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output logic [31:0] InstrM, // The decoded instruction in Memory stage
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output logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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output logic [P.XLEN-1:0] PCM, // Memory stage instruction address
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// branch predictor
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output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
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output logic BPDirPredWrongM, // Prediction direction is wrong
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output logic BTAWrongM, // Prediction target wrong
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output logic RASPredPCWrongM, // RAS prediction is wrong
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output logic IClassWrongM, // Class prediction is wrong
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output logic ICacheStallF, // I$ busy with multicycle operation
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output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
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output logic BPDirPredWrongM, // Prediction direction is wrong
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output logic BTAWrongM, // Prediction target wrong
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output logic RASPredPCWrongM, // RAS prediction is wrong
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output logic IClassWrongM, // Class prediction is wrong
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output logic ICacheStallF, // I$ busy with multicycle operation
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// Faults
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input logic IllegalBaseInstrD, // Illegal non-compressed instruction
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input logic IllegalFPUInstrD, // Illegal FP instruction
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output logic InstrPageFaultF, // Instruction page fault
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output logic IllegalIEUFPUInstrD, // Illegal instruction including compressed & FP
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output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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input logic IllegalBaseInstrD, // Illegal non-compressed instruction
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input logic IllegalFPUInstrD, // Illegal FP instruction
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output logic InstrPageFaultF, // Instruction page fault
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output logic IllegalIEUFPUInstrD, // Illegal instruction including compressed & FP
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output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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// mmu management
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input logic [1:0] PrivilegeModeW, // Priviledge mode in Writeback stage
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input logic [1:0] PrivilegeModeW, // Priviledge mode in Writeback stage
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input logic [P.XLEN-1:0] PTE, // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
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input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB
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input logic ITLBWriteF, // Writes PTE and PageType to ITLB
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input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB
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input logic ITLBWriteF, // Writes PTE and PageType to ITLB
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input logic [P.XLEN-1:0] SATP_REGW, // Location of the root page table and page table configuration
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input logic STATUS_MXR, // Status CSR: make executable page readable
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input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
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input logic STATUS_MPRV, // Status CSR: modify machine privilege
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input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
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input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP address from privileged unit
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output logic InstrAccessFaultF, // Instruction access fault
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output logic ICacheAccess, // Report I$ read to performance counters
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output logic ICacheMiss // Report I$ miss to performance counters
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input logic STATUS_MXR, // Status CSR: make executable page readable
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input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
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input logic STATUS_MPRV, // Status CSR: modify machine privilege
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input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
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input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit
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output logic InstrAccessFaultF, // Instruction access fault
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output logic ICacheAccess, // Report I$ read to performance counters
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output logic ICacheMiss // Report I$ miss to performance counters
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);
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic [P.XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
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logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
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logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
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logic [P.XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j)
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logic [P.XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
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logic [P.XLEN-1:0] PCD; // Decode stage instruction address
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logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
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logic [P.XLEN-1:0] PCF; // Fetch stage instruction address
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logic [P.PA_BITS-1:0] PCPF; // Physical address after address translation
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logic [P.XLEN+1:0] PCFExt; //
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logic [P.XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
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logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
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logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
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logic [P.XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j)
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logic [P.XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
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logic [P.XLEN-1:0] PCD; // Decode stage instruction address
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logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
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logic [P.XLEN-1:0] PCF; // Fetch stage instruction address
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logic [P.PA_BITS-1:0] PCPF; // Physical address after address translation
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logic [P.XLEN+1:0] PCFExt;
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logic [31:0] IROMInstrF; // Instruction from the IROM
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logic [31:0] ICacheInstrF; // Instruction from the I$
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logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus
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logic CompressedF; // The fetched instruction is compressed
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logic CompressedD; // The decoded instruction is compressed
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logic CompressedE; // The execution instruction is compressed
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logic CompressedM; // The execution instruction is compressed
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logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
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logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage
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logic IllegalIEUInstrD; // IEU Instruction (regular or compressed) is not good
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logic [31:0] IROMInstrF; // Instruction from the IROM
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logic [31:0] ICacheInstrF; // Instruction from the I$
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logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus
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logic CompressedF; // The fetched instruction is compressed
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logic CompressedD; // The decoded instruction is compressed
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logic CompressedE; // The execution instruction is compressed
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logic CompressedM; // The execution instruction is compressed
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logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
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logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage
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logic IllegalIEUInstrD; // IEU Instruction (regular or compressed) is not good
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logic [1:0] IFURWF; // IFU alreays read IFURWF = 10
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logic [31:0] InstrE; // Instruction in the Execution stage
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logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush
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logic [1:0] IFURWF; // IFU alreays read IFURWF = 10
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logic [31:0] InstrE; // Instruction in the Execution stage
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logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush
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logic CacheableF; // PMA indicates instruction address is cacheable
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logic SelSpillNextF; // In a spill, stall pipeline and gate local stallF
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logic BusStall; // Bus interface busy with multicycle operation
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logic IFUCacheBusStallF; // EIther I$ or bus busy with multicycle operation
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logic GatedStallD; // StallD gated by selected next spill
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logic CacheableF; // PMA indicates instruction address is cacheable
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logic SelSpillNextF; // In a spill, stall pipeline and gate local stallF
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logic BusStall; // Bus interface busy with multicycle operation
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logic IFUCacheBusStallF; // EIther I$ or bus busy with multicycle operation
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logic GatedStallD; // StallD gated by selected next spill
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// branch predictor signal
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logic [P.XLEN-1:0] PC1NextF; // Branch predictor next PCF
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logic BusCommittedF; // Bus memory operation in flight, delay interrupts
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logic CacheCommittedF; // I$ memory operation started, delay interrupts
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logic SelIROM; // PMA indicates instruction address is in the IROM
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logic [15:0] InstrRawE, InstrRawM;
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logic [P.XLEN-1:0] PC1NextF; // Branch predictor next PCF
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logic BusCommittedF; // Bus memory operation in flight, delay interrupts
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logic CacheCommittedF; // I$ memory operation started, delay interrupts
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logic SelIROM; // PMA indicates instruction address is in the IROM
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logic [15:0] InstrRawE, InstrRawM;
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assign PCFExt = {2'b00, PCSpillF};
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@ -199,6 +198,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Memory
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////////////////////////////////////////////////////////////////////////////////////////////////
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// CommittedM tells the CPU's privileged unit the current instruction
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// in the memory stage is a memory operaton and that memory operation is either completed
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// or is partially executed. Partially completed memory operations need to prevent an interrupts.
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@ -206,7 +206,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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// delay the interrupt until the LSU is in a clean state.
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assign CommittedF = CacheCommittedF | BusCommittedF;
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logic IgnoreRequest;
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logic IgnoreRequest;
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assign IgnoreRequest = ITLBMissF | FlushD;
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// The IROM uses untranslated addresses, so it is not compatible with virtual memory.
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@ -223,12 +223,12 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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localparam WORDSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.XLEN : 1;
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localparam LOGBWPL = P.ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1;
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if(P.ICACHE_SUPPORTED) begin : icache
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localparam LINELEN = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS : P.XLEN;
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localparam LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
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logic [LINELEN-1:0] FetchBuffer;
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localparam LINELEN = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS : P.XLEN;
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localparam LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
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logic [LINELEN-1:0] FetchBuffer;
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logic [P.PA_BITS-1:0] ICacheBusAdr;
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logic ICacheBusAck;
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logic [1:0] CacheBusRW, BusRW, CacheRWF;
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logic ICacheBusAck;
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logic [1:0] CacheBusRW, BusRW, CacheRWF;
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assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
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assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
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@ -255,7 +255,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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.Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
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.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
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.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
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.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
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.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
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.FetchBuffer, .PAdr(PCPF),
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.BusRW, .Stall(GatedStallD),
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.BusStall, .BusCommitted(BusCommittedF));
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@ -321,7 +321,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
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else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Branch and Jump Predictor
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////////////////////////////////////////////////////////////////////////////////////////////////
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@ -341,10 +340,10 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign NextValidPCE = PCE;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Decode stage pipeline register and compressed instruction decoding.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Decode stage pipeline register and logic
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flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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@ -374,10 +373,10 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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// Instruction and PC/PCLink pipeline registers
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// Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.
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mux2 #(32) FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
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mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
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flopenr #(32) InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
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flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
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mux2 #(32) FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
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mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
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flopenr #(32) InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
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flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
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flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
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flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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//flopenr #(P.XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
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