mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Found a whole bunch of files still using the old `define configurations.
This commit is contained in:
Ross Thompson
parent
301d54fea8
commit
b8a243827b
4
src/cache/cache.sv
vendored
4
src/cache/cache.sv
vendored
@ -27,7 +27,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
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module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, USE_SRAM, READ_ONLY_CACHE) (
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input logic clk,
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input logic reset,
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input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
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@ -112,7 +112,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, W
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AdrSelMuxSel, CacheSet);
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
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cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, USE_SRAM, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
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.clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask,
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.SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
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6
src/cache/cacheway.sv
vendored
6
src/cache/cacheway.sv
vendored
@ -28,7 +28,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26,
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OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
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OFFSETLEN = 5, INDEXLEN = 9, USE_SRAM = 1, READ_ONLY_CACHE = 0) (
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input logic clk,
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input logic reset,
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input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
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@ -109,7 +109,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
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// Tag Array
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/////////////////////////////////////////////////////////////////////////////////////////////
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ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
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ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN), .USE_SRAM(USE_SRAM)) CacheTagMem(.clk, .ce(CacheEn),
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.addr(CacheSet), .dout(ReadTag),
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.din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
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@ -137,7 +137,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
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.we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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end
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else begin:wordram // no byte-enable needed for i$.
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ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
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ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN), .USE_SRAM(USE_SRAM)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
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.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.we(SelectedWriteWordEn));
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module flop #(parameter WIDTH = 8) (
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input logic clk,
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input logic [WIDTH-1:0] d,
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module flopen #(parameter WIDTH = 8) (
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input logic clk, en,
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input logic [WIDTH-1:0] d,
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
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input logic clk, load, en,
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input TYPE d,
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module flopenr #(parameter WIDTH = 8) (
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input logic clk, reset, en,
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input logic [WIDTH-1:0] d,
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module flopenrc #(parameter WIDTH = 8) (
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input logic clk, reset, clear, en,
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input logic [WIDTH-1:0] d,
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module flopens #(parameter WIDTH = 8) (
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input logic clk, set, en,
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input logic [WIDTH-1:0] d,
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module flopr #(parameter WIDTH = 8) (
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input logic clk, reset,
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input logic [WIDTH-1:0] d,
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module floprc #(parameter WIDTH = 8) (
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input logic clk,
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input logic reset,
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@ -24,8 +24,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module synchronizer (
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input logic clk,
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input logic d,
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@ -30,11 +30,11 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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`include "wally-config.vh"
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module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) (
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input logic clk,
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input logic ce,
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input logic [$clog2(DEPTH)-1:0] addr,
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@ -30,9 +30,7 @@
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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`include "wally-config.vh"
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module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
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module ram1p1rwe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) (
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input logic clk,
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input logic ce,
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input logic [$clog2(DEPTH)-1:0] addr,
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@ -46,19 +44,19 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
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// ***************************************************************************
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// TRUE SRAM macro
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// ***************************************************************************
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if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
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if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
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// 64 x 128-bit SRAM
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ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
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.A(addr), .D(din),
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.BWEB('0), .Q(dout));
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end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag
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end else if ((USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag
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// 64 x 44-bit SRAM
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ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
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.A(addr), .D(din),
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.BWEB('0), .Q(dout));
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end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag
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end else if ((USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag
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// 64 x 22-bit SRAM
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ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
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.A(addr), .D(din),
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@ -29,11 +29,11 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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`include "wally-config.vh"
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module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) (
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input logic clk,
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input logic ce1, ce2,
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input logic [$clog2(DEPTH)-1:0] ra1,
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@ -52,7 +52,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
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// TRUE Smem macro
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// ***************************************************************************
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if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
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if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
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ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk),
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.CEBA(~ce1), .CEBB(~ce2),
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@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
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.QA(rd1),
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.QB());
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end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
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end else if ((USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
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ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk),
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.CEBA(~ce1), .CEBB(~ce2),
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@ -25,8 +25,6 @@
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// This model actually works correctly with vivado.
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`include "wally-config.vh"
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module rom1p1r #(parameter ADDR_WIDTH = 8,
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parameter DATA_WIDTH = 32,
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parameter PRELOAD_ENABLED = 0)
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@ -29,7 +29,7 @@
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`include "wally-config.vh"
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module alu #(parameter WIDTH=32) (
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module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic W64, // W64-type instruction
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input logic SubArith, // Subtraction or arithmetic shift
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@ -56,7 +56,7 @@ module alu #(parameter WIDTH=32) (
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assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
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// Shifts (configurable for rotation)
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shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
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shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
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// Condition code flags are based on subtraction output Sum = A-B.
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// Overflow occurs when the numbers being subtracted have the opposite sign
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@ -76,7 +76,7 @@ module alu #(parameter WIDTH=32) (
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3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt
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3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu
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3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv
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3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
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3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
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3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
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3'b111: FullResult = A & CondMaskInvB; // and, bclr
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endcase
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@ -87,8 +87,8 @@ module alu #(parameter WIDTH=32) (
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else assign PreALUResult = FullResult;
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// Final Result B instruction select mux
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if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
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bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
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if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu
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bitmanipalu #(P, WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
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.Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .ALUResult);
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end else begin
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@ -96,4 +96,4 @@ module alu #(parameter WIDTH=32) (
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assign CondMaskB = B;
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assign CondShiftA = A;
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end
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endmodule
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endmodule
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@ -27,9 +27,8 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module bitmanipalu #(parameter WIDTH=32) (
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module bitmanipalu import cvw::*; #(parameter cvw_t P,
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parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic W64, // W64-type instruction
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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@ -56,13 +55,13 @@ module bitmanipalu #(parameter WIDTH=32) (
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assign {Mask, PreShift} = BALUControl[1:0];
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// Mask Generation Mux
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if (`ZBS_SUPPORTED) begin: zbsdec
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if (P.ZBS_SUPPORTED) begin: zbsdec
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decoder #($clog2(WIDTH)) maskgen(B[$clog2(WIDTH)-1:0], MaskB);
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mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB);
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end else assign CondMaskB = B;
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// 0-3 bit Pre-Shift Mux
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if (`ZBA_SUPPORTED) begin: zbapreshift
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if (P.ZBA_SUPPORTED) begin: zbapreshift
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if (WIDTH == 64) begin
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mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA);
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end else assign CondZextA = A;
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@ -74,12 +73,12 @@ module bitmanipalu #(parameter WIDTH=32) (
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end
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// Bit reverse needed for some ZBB, ZBC instructions
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if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse
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if (P.ZBC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
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bitreverse #(WIDTH) brA(.A, .RevA);
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end
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// ZBC Unit
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if (`ZBC_SUPPORTED) begin: zbc
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if (P.ZBC_SUPPORTED) begin: zbc
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logic ZBCSelect; // ZBC instruction
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assign ZBCSelect = BSelect == 2'b11;
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//assign ZBCSelect = 1'b0;
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@ -87,7 +86,7 @@ module bitmanipalu #(parameter WIDTH=32) (
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end else assign ZBCResult = 0;
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// ZBB Unit
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if (`ZBB_SUPPORTED) begin: zbb
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if (P.ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
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end else assign ZBBResult = 0;
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@ -27,7 +27,6 @@
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module bitreverse #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A,
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@ -27,8 +27,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module byteop #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, // Operands
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input logic ByteSelect, // LSB of Immediate
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@ -43,4 +41,4 @@ module byteop #(parameter WIDTH=32) (
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end
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mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult);
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endmodule
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endmodule
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@ -27,8 +27,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module clmul #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] X, Y, // Operands
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output logic [WIDTH-1:0] ClmulResult); // ZBS result
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@ -28,8 +28,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cnt #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] A, RevA, // Operands
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input logic [1:0] B, // Last 2 bits of immediate
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@ -62,4 +60,4 @@ module cnt #(parameter WIDTH = 32) (
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assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0;
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mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult);
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endmodule
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endmodule
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@ -28,8 +28,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ext #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] A, // Operands
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input logic [1:0] ExtSelect, // B[2], B[0] of immediate
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@ -42,4 +40,4 @@ module ext #(parameter WIDTH = 32) (
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assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]};
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mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult);
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endmodule
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endmodule
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|
||||
@ -28,8 +28,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module zbb #(parameter WIDTH=32) (
|
||||
input logic [WIDTH-1:0] A, RevA, B, // Operands
|
||||
input logic W64, // Indicates word operation
|
||||
@ -55,4 +53,4 @@ module zbb #(parameter WIDTH=32) (
|
||||
|
||||
// ZBB Result select mux
|
||||
mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult);
|
||||
endmodule
|
||||
endmodule
|
||||
|
||||
@ -27,8 +27,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module zbc #(parameter WIDTH=32) (
|
||||
input logic [WIDTH-1:0] A, RevA, B, // Operands
|
||||
input logic ZBCSelect, // ZBC instruction
|
||||
|
||||
@ -27,8 +27,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
// This comparator is best
|
||||
module comparator #(parameter WIDTH=64) (
|
||||
input logic [WIDTH-1:0] a, b, // Operands
|
||||
|
||||
@ -112,7 +112,7 @@ module datapath import cvw::*; #(parameter cvw_t P) (
|
||||
comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
|
||||
mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
|
||||
mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
|
||||
alu #(P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE);
|
||||
alu #(P, P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE);
|
||||
mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
|
||||
mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
|
||||
|
||||
|
||||
@ -27,21 +27,19 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module shifter (
|
||||
input logic [`XLEN-1:0] A, // shift Source
|
||||
input logic [`LOG_XLEN-1:0] Amt, // Shift amount
|
||||
module shifter import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.XLEN-1:0] A, // shift Source
|
||||
input logic [P.LOG_XLEN-1:0] Amt, // Shift amount
|
||||
input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift
|
||||
output logic [`XLEN-1:0] Y); // Shifted result
|
||||
output logic [P.XLEN-1:0] Y); // Shifted result
|
||||
|
||||
logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
|
||||
logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount
|
||||
logic [2*P.XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
|
||||
logic [P.LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount
|
||||
logic Sign; // Sign bit for sign extension
|
||||
|
||||
assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension
|
||||
if (`XLEN==32) begin // rv32
|
||||
if (`ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
|
||||
assign Sign = A[P.XLEN-1] & SubArith; // sign bit for sign extension
|
||||
if (P.XLEN==32) begin // rv32
|
||||
if (P.ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
|
||||
always_comb // funnel mux
|
||||
case({Right, Rotate})
|
||||
2'b00: Z = {A[31:0], 31'b0};
|
||||
@ -56,12 +54,12 @@ module shifter (
|
||||
end
|
||||
assign TruncAmt = Amt; // shift amount
|
||||
end else begin // rv64
|
||||
logic [`XLEN-1:0] A64;
|
||||
logic [P.XLEN-1:0] A64;
|
||||
mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
|
||||
if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
|
||||
if (P.ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
|
||||
// shifter rotate source select mux
|
||||
logic [`XLEN-1:0] RotA; // rotate source
|
||||
mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
|
||||
logic [P.XLEN-1:0] RotA; // rotate source
|
||||
mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
|
||||
always_comb // funnel mux
|
||||
case ({Right, Rotate})
|
||||
2'b00: Z = {A64[63:0],{63'b0}};
|
||||
@ -82,7 +80,7 @@ module shifter (
|
||||
|
||||
// Funnel operation
|
||||
assign ZShift = Z >> Offset;
|
||||
assign Y = ZShift[`XLEN-1:0];
|
||||
assign Y = ZShift[P.XLEN-1:0];
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@ -92,7 +92,7 @@ module btb import cvw::*; #(parameter cvw_t P,
|
||||
|
||||
|
||||
// An optimization may be using a PC relative address.
|
||||
ram2p1r1wbe #(2**Depth, P.XLEN+4) memory(
|
||||
ram2p1r1wbe #(2**Depth, P.XLEN+4, P.USE_SRAM) memory(
|
||||
.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
|
||||
.ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
|
||||
|
||||
|
||||
@ -30,7 +30,8 @@
|
||||
|
||||
module gshare #(parameter XLEN,
|
||||
parameter k = 10,
|
||||
parameter integer TYPE = 1) (
|
||||
parameter integer TYPE = 1,
|
||||
parameter USE_SRAM = 1) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
@ -83,7 +84,7 @@ module gshare #(parameter XLEN,
|
||||
|
||||
assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF;
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableBPDirPredF),
|
||||
|
||||
@ -29,7 +29,8 @@
|
||||
|
||||
module gsharebasic #(parameter XLEN,
|
||||
parameter k = 10,
|
||||
parameter TYPE = 1) (
|
||||
parameter TYPE = 1,
|
||||
parameter USE_SRAM = 1) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
@ -57,7 +58,7 @@ module gsharebasic #(parameter XLEN,
|
||||
assign IndexM = GHRM;
|
||||
end
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(BPDirPredF),
|
||||
|
||||
@ -27,7 +27,8 @@
|
||||
|
||||
module localaheadbp #(parameter XLEN,
|
||||
parameter m = 6, // 2^m = number of local history branches
|
||||
parameter k = 10) ( // number of past branches stored
|
||||
parameter k = 10,
|
||||
parameter USE_SRAM = 1) ( // number of past branches stored
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
@ -58,7 +59,7 @@ module localaheadbp #(parameter XLEN,
|
||||
//assign IndexNextF = LHR;
|
||||
assign IndexM = LHRW;
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk),
|
||||
.ce1(~StallD), .ce2(~StallW & ~FlushW),
|
||||
.ra1(LHRF),
|
||||
.rd1(BPDirPredD),
|
||||
@ -91,7 +92,7 @@ module localaheadbp #(parameter XLEN,
|
||||
assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
|
||||
assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
|
||||
|
||||
ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexLHRNextF),
|
||||
.rd1(LHRF),
|
||||
|
||||
@ -28,7 +28,8 @@
|
||||
|
||||
module localbpbasic #(parameter XLEN,
|
||||
parameter m = 6, // 2^m = number of local history branches
|
||||
parameter k = 10) ( // number of past branches stored
|
||||
parameter k = 10,
|
||||
parameter USE_SRAM = 1) ( // number of past branches stored
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
@ -55,7 +56,7 @@ module localbpbasic #(parameter XLEN,
|
||||
assign IndexNextF = LHR;
|
||||
assign IndexM = LHRM;
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(BPDirPredF),
|
||||
|
||||
@ -27,7 +27,8 @@
|
||||
|
||||
module localrepairbp #(parameter XLEN,
|
||||
parameter m = 6, // 2^m = number of local history branches
|
||||
parameter k = 10) ( // number of past branches stored
|
||||
parameter k = 10,
|
||||
parameter USE_SRAM = 1) ( // number of past branches stored
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
@ -57,7 +58,7 @@ module localrepairbp #(parameter XLEN,
|
||||
logic SpeculativeFlushedF;
|
||||
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk),
|
||||
.ce1(~StallD), .ce2(~StallW & ~FlushW),
|
||||
.ra1(LHRF),
|
||||
.rd1(BPDirPredD),
|
||||
@ -88,7 +89,7 @@ module localrepairbp #(parameter XLEN,
|
||||
assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
|
||||
assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
|
||||
|
||||
ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexLHRNextF),
|
||||
.rd1(LHRCommittedF),
|
||||
|
||||
@ -27,7 +27,8 @@
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module twoBitPredictor #(parameter XLEN,
|
||||
parameter k = 10) (
|
||||
parameter k = 10,
|
||||
parameter USE_SRAM = 1) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
@ -53,7 +54,7 @@ module twoBitPredictor #(parameter XLEN,
|
||||
assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(BPDirPredF),
|
||||
|
||||
@ -29,7 +29,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module decompress #(parameter XLEN)(
|
||||
input logic [31:0] InstrRawD, // 32-bit instruction or raw compressed 16-bit instruction in bottom half
|
||||
@ -91,18 +90,18 @@ module decompress #(parameter XLEN)(
|
||||
end
|
||||
5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
|
||||
5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
|
||||
5'b00011: if (`XLEN==32)
|
||||
5'b00011: if (XLEN==32)
|
||||
InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
|
||||
else
|
||||
InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
|
||||
5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
|
||||
5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
|
||||
5'b00111: if (`XLEN==32)
|
||||
5'b00111: if (XLEN==32)
|
||||
InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
|
||||
else
|
||||
InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
|
||||
5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
|
||||
5'b01001: if (`XLEN==32)
|
||||
5'b01001: if (XLEN==32)
|
||||
InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
|
||||
else
|
||||
InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
|
||||
@ -126,7 +125,7 @@ module decompress #(parameter XLEN)(
|
||||
InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
|
||||
else // if (instr16[6:5] == 2'b11)
|
||||
InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
|
||||
else if (`XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10]
|
||||
else if (XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10]
|
||||
if (instr16[6:5] == 2'b00)
|
||||
InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
|
||||
else if (instr16[6:5] == 2'b01)
|
||||
@ -151,7 +150,7 @@ module decompress #(parameter XLEN)(
|
||||
5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
|
||||
5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
|
||||
5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
|
||||
5'b10011: if (`XLEN == 32)
|
||||
5'b10011: if (XLEN == 32)
|
||||
InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
|
||||
else
|
||||
InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
|
||||
@ -170,7 +169,7 @@ module decompress #(parameter XLEN)(
|
||||
InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
|
||||
5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
|
||||
5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
|
||||
5'b10111: if (`XLEN==32)
|
||||
5'b10111: if (XLEN==32)
|
||||
InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
|
||||
else
|
||||
InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
|
||||
|
||||
@ -234,7 +234,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
||||
assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
|
||||
cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
|
||||
.NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
|
||||
.NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
|
||||
.NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .USE_SRAM(P.USE_SRAM), .READ_ONLY_CACHE(1))
|
||||
icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
|
||||
.FetchBuffer, .CacheBusAck(ICacheBusAck),
|
||||
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
|
||||
|
||||
@ -29,8 +29,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module spill import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
|
||||
@ -49,7 +49,7 @@ module dtim import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap.
|
||||
|
||||
ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN))
|
||||
ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN), .USE_SRAM(P.USE_SRAM))
|
||||
ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
|
||||
endmodule
|
||||
|
||||
|
||||
@ -262,7 +262,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
||||
assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW);
|
||||
|
||||
cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
|
||||
.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
|
||||
.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .USE_SRAM(P.USE_SRAM), .READ_ONLY_CACHE(0)) dcache(
|
||||
.clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
|
||||
.FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM),
|
||||
.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
|
||||
|
||||
@ -105,7 +105,7 @@ module div import cvw::*; #(parameter cvw_t P) (
|
||||
// one copy of divstep for each bit produced per cycle
|
||||
genvar i;
|
||||
for (i=0; i<P.IDIV_BITSPERCYCLE; i = i+1)
|
||||
divstep divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
|
||||
divstep #(P.XLEN) divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
|
||||
|
||||
//////////////////////////////
|
||||
// Memory Stage: output sign correction and special cases
|
||||
|
||||
@ -26,26 +26,24 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
/* verilator lint_off UNOPTFLAT */
|
||||
|
||||
module divstep(
|
||||
input logic [`XLEN-1:0] W, // Residual in
|
||||
input logic [`XLEN-1:0] XQ, // bits of dividend X and quotient Q in
|
||||
input logic [`XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
|
||||
output logic [`XLEN-1:0] WOut, // Residual out
|
||||
output logic [`XLEN-1:0] XQOut // bits of dividend and quotient out: discard one bit of X, append one bit of Q
|
||||
module divstep #(parameter XLEN) (
|
||||
input logic [XLEN-1:0] W, // Residual in
|
||||
input logic [XLEN-1:0] XQ, // bits of dividend X and quotient Q in
|
||||
input logic [XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
|
||||
output logic [XLEN-1:0] WOut, // Residual out
|
||||
output logic [XLEN-1:0] XQOut // bits of dividend and quotient out: discard one bit of X, append one bit of Q
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] WShift; // Shift W left by one bit, bringing in most significant bit of X
|
||||
logic [`XLEN-1:0] WPrime; // WShift - D, for comparison and possible result
|
||||
logic [XLEN-1:0] WShift; // Shift W left by one bit, bringing in most significant bit of X
|
||||
logic [XLEN-1:0] WPrime; // WShift - D, for comparison and possible result
|
||||
logic qi, qib; // Quotient digit and its complement
|
||||
|
||||
assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi}; // shift W and X/Q left, insert quotient bit at bottom
|
||||
adder #(`XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
|
||||
assign {WShift, XQOut} = {W[XLEN-2:0], XQ, qi}; // shift W and X/Q left, insert quotient bit at bottom
|
||||
adder #(XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
|
||||
assign qi = ~qib;
|
||||
mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
|
||||
mux2 #(XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
|
||||
endmodule
|
||||
|
||||
/* verilator lint_on UNOPTFLAT */
|
||||
|
||||
@ -26,8 +26,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module vm64check import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.SVMODE_BITS-1:0] SATP_MODE,
|
||||
input logic [P.XLEN-1:0] VAdr,
|
||||
|
||||
@ -19,45 +19,43 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module riscvassertions;
|
||||
module riscvassertions import cvw::*; #(parameter cvw_t P);
|
||||
initial begin
|
||||
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`S_SUPPORTED || `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
|
||||
assert (`IDIV_BITSPERCYCLE == 1 || `IDIV_BITSPERCYCLE==2 || `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
|
||||
assert (`D_SUPPORTED || ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
|
||||
assert (`F_SUPPORTED || ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
|
||||
assert (`DCACHE_SUPPORTED || ~`F_SUPPORTED || `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
|
||||
assert (`FLEN<=`XLEN || `DCACHE_SUPPORTED || `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || (!`DCACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_LINELENINBITS >= 128 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || (!`ICACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_LINELENINBITS >= 32 || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES || (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES || (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
|
||||
assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
|
||||
assert (`ZICSR_SUPPORTED == 1 || (`S_SUPPORTED == 0 && `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
|
||||
assert (`U_SUPPORTED || (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
assert (`VIRTMEM_SUPPORTED == 0 || (`DTIM_SUPPORTED == 0 && `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||
assert (`DCACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (`ICACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
assert ((`DCACHE_SUPPORTED == 0 && `ICACHE_SUPPORTED == 0) || `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
|
||||
assert (`DCACHE_LINELENINBITS <= `XLEN*16 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
|
||||
assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
||||
assert (`DCACHE_SUPPORTED || (`A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally.");
|
||||
assert (`IDIV_ON_FPU == 0 || `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
|
||||
assert (`SSTC_SUPPORTED == 0 || (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
|
||||
assert ((`ZMMUL_SUPPORTED == 0) || (`M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
|
||||
assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
|
||||
assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
|
||||
assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
|
||||
assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
|
||||
assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||
assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported");
|
||||
assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
|
||||
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (P.UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
|
||||
assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
|
||||
assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
|
||||
assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||
assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
|
||||
assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
|
||||
assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
||||
assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally.");
|
||||
assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
|
||||
assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
|
||||
assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -88,7 +88,7 @@ module testbench;
|
||||
logic SelectTest;
|
||||
|
||||
// check assertions for a legal configuration
|
||||
riscvassertions riscvassertions();
|
||||
riscvassertions #(P) riscvassertions();
|
||||
|
||||
// pick tests based on modes supported
|
||||
initial begin
|
||||
|
||||
Loading…
Reference in New Issue
Block a user