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https://github.com/openhwgroup/cvw
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Fixed formatting
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Harshini Srinath
GitHub
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commit
8e97224cd7
@ -27,50 +27,50 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module flags import cvw::*; #(parameter cvw_t P) (
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input logic Xs, // X sign
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input logic Xs, // X sign
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input logic [P.FMTBITS-1:0] OutFmt, // output format
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input logic InfIn, // is a Inf input being used
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input logic XInf, YInf, ZInf, // inputs are infinity
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input logic NaNIn, // is a NaN input being used
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input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
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input logic XZero, YZero, // inputs are zero
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input logic InfIn, // is a Inf input being used
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input logic XInf, YInf, ZInf, // inputs are infinity
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input logic NaNIn, // is a NaN input being used
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input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
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input logic XZero, YZero, // inputs are zero
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input logic [P.NE+1:0] FullRe, // Re with bits to determine sign and overflow
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input logic [P.NE+1:0] Me, // exponent of the normalized sum
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// rounding
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input logic Plus1, // do you add one for rounding
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input logic Round, Guard, Sticky, // bits used to determine rounding
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input logic UfPlus1, // do you add one for rounding for the unbounded exponent result
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input logic Plus1, // do you add one for rounding
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input logic Round, Guard, Sticky, // bits used to determine rounding
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input logic UfPlus1, // do you add one for rounding for the unbounded exponent result
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// convert
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input logic CvtOp, // conversion opperation?
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input logic ToInt, // convert to integer
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input logic IntToFp, // convert integer to floating point
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input logic Int64, // convert to 64 bit integer
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input logic Signed, // convert to a signed integer
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input logic CvtOp, // conversion opperation?
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input logic ToInt, // convert to integer
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input logic IntToFp, // convert integer to floating point
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input logic Int64, // convert to 64 bit integer
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input logic Signed, // convert to a signed integer
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input logic [P.NE:0] CvtCe, // the calculated expoent - Cvt
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input logic [1:0] CvtNegResMsbs, // the negitive integer result's most significant bits
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input logic [1:0] CvtNegResMsbs, // the negitive integer result's most significant bits
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// divsqrt
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input logic DivOp, // conversion opperation?
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input logic Sqrt, // Sqrt?
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input logic DivOp, // conversion opperation?
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input logic Sqrt, // Sqrt?
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// fma
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input logic FmaOp, // Fma opperation?
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input logic FmaAs, FmaPs, // the product and modified Z signs
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input logic FmaOp, // Fma opperation?
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input logic FmaAs, FmaPs, // the product and modified Z signs
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// flags
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output logic DivByZero, // divide by zero flag
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output logic Overflow, // overflow flag to select result
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output logic Invalid, // invalid flag to select the result
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output logic IntInvalid, // invalid integer result to select
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output logic [4:0] PostProcFlg // flags
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output logic DivByZero, // divide by zero flag
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output logic Overflow, // overflow flag to select result
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output logic Invalid, // invalid flag to select the result
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output logic IntInvalid, // invalid integer result to select
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output logic [4:0] PostProcFlg // flags
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);
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logic SigNaN; // is an input a signaling NaN
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logic Inexact; // final inexact flag
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logic FpInexact; // floating point inexact flag
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logic IntInexact; // integer inexact flag
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logic FmaInvalid; // integer invalid flag
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logic DivInvalid; // integer invalid flag
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logic Underflow; // Underflow flag
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logic ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent
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logic ShiftGtIntSz; // is the shift greater than the the integer size (use Re to account for possible roundning "shift")
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logic SigNaN; // is an input a signaling NaN
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logic Inexact; // final inexact flag
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logic FpInexact; // floating point inexact flag
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logic IntInexact; // integer inexact flag
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logic FmaInvalid; // integer invalid flag
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logic DivInvalid; // integer invalid flag
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logic Underflow; // Underflow flag
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logic ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent
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logic ShiftGtIntSz; // is the shift greater than the the integer size (use Re to account for possible roundning "shift")
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///////////////////////////////////////////////////////////////////////////////
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// Overflow
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@ -86,7 +86,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
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// 65 = ...0 0 0 0 0 1 0 0 0 0 0 1
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// | or | | or |
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// 33 = ...0 0 0 0 0 0 1 0 0 0 0 1
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// | or | | or |
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// | or | | or |
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// larger or equal if:
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// - any of the bits after the most significan 1 is one
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// - the most signifcant in 65 or 33 is still a one in the number and
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@ -102,9 +102,9 @@ module flags import cvw::*; #(parameter cvw_t P) (
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end else if (P.FPSIZES == 3) begin
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always_comb
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case (OutFmt)
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P.FMT: ResExpGteMax = &FullRe[P.NE-1:0] | FullRe[P.NE];
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P.FMT1: ResExpGteMax = &FullRe[P.NE1-1:0] | (|FullRe[P.NE:P.NE1]);
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P.FMT2: ResExpGteMax = &FullRe[P.NE2-1:0] | (|FullRe[P.NE:P.NE2]);
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P.FMT: ResExpGteMax = &FullRe[P.NE-1:0] | FullRe[P.NE];
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P.FMT1: ResExpGteMax = &FullRe[P.NE1-1:0] | (|FullRe[P.NE:P.NE1]);
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P.FMT2: ResExpGteMax = &FullRe[P.NE2-1:0] | (|FullRe[P.NE:P.NE2]);
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default: ResExpGteMax = 1'bx;
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endcase
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assign ShiftGtIntSz = (|FullRe[P.NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
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@ -119,8 +119,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
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endcase
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assign ShiftGtIntSz = (|FullRe[P.Q_NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
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end
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// calulate overflow flag:
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// if the result is greater than or equal to the max exponent(not taking into account sign)
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// | and the exponent isn't negitive
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@ -142,7 +141,6 @@ module flags import cvw::*; #(parameter cvw_t P) (
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// | | | | | |
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assign Underflow = ((FullRe[P.NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&Guard)))&(Round|Sticky|Guard))&~(InfIn|NaNIn|DivByZero|Invalid);
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///////////////////////////////////////////////////////////////////////////////
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// Inexact
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///////////////////////////////////////////////////////////////////////////////
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@ -199,7 +197,6 @@ module flags import cvw::*; #(parameter cvw_t P) (
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// - don't set flag if an input is NaN or Inf(IEEE says has to be a finite numerator)
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assign DivByZero = YZero&DivOp&~Sqrt&~(XZero|NaNIn|InfIn);
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///////////////////////////////////////////////////////////////////////////////
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// final flags
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///////////////////////////////////////////////////////////////////////////////
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@ -209,7 +206,3 @@ module flags import cvw::*; #(parameter cvw_t P) (
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assign PostProcFlg = {Invalid|(IntInvalid&CvtOp&ToInt), DivByZero, Overflow&~(ToInt&CvtOp), Underflow&~(ToInt&CvtOp), Inexact};
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endmodule
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